Applications Engineer - Silicon IP

Job Title

Applications Engineer - Silicon IP

Role Summary

Customer-facing applications engineer responsible for helping customers evaluate, integrate, verify, and implement Efficient's silicon IP into their SoCs. Acts as the technical bridge between customers and internal design, verification, physical design, and characterization teams to resolve integration issues and keep tapeouts on schedule.

Experience Level

Mid-level. Typical candidate has 5+ years of experience in ASIC/SoC verification, physical design, silicon IP integration, or a closely related applications engineering role.

Responsibilities

Provide technical support and enablement throughout IP integration, from verification to signoff.

• Serve as primary technical contact for customers integrating IP: RTL simulation, UVM testbenches, synthesis, floorplan, P&R, STA, and signoff.
• Debug integration issues across RTL, testbench, constraints, and physical implementation; identify root cause and corrective actions.
• Develop and maintain reference verification environments, example flows, SDC/UPF templates, and floorplan guidance.
• Deliver remote and onsite technical training on IP architecture, verification methodology, and implementation best practices.
• Support pre-sales technical evaluations (PPA, verification collateral, node/process readiness, integration effort).
• Lead architecture-to-signoff reviews, identify implementation risks, and recommend mitigations.
• Convert recurring support cases into reusable enablement: diagnostic playbooks, automation, and self-service guidance.
• Track and report field issues and integration patterns to inform product roadmap and release quality.

Requirements

Must-have technical skills and experience for immediate effectiveness in the role.

• 5+ years of hands-on experience in ASIC/SoC verification, physical design, silicon IP integration, or a similar applications role.
• Strong scripting and automation skills (Python, TCL, Make, shell) for building flows, regressions, and debug tooling.
• Practical experience integrating soft/hard macros, interface/protocol IP, interconnect, standard-cell libraries, or memory compilers.
• Proven ability to diagnose complex integration issues and produce clear, actionable guidance for customers and internal teams.
• Familiarity with multiple foundries/process nodes and the verification, PPA, reliability, and signoff challenges they introduce.
• Experience with SystemVerilog/UVM and reading/debugging RTL, and/or experience with synthesis, floorplanning, P&R, and STA.
• Working knowledge of timing models and physical abstracts (Liberty/ECSM/CCS, LEF), constraints and low-power intent (SDC, UPF), and signoff flows (STA, IR/EM, DRC/LVS).
• Willingness to travel to customer sites approximately 20–30% depending on business needs.

Nice-to-have:

• Background as an IP vendor applications engineer, verification or physical-design consultant, or silicon IP integrator at a systems/SoC company.
• Experience with formal verification, verification IP, low-power design, SoC-level DFT, reliability signoff, or high-speed interfaces.
• Experience delivering technical training or conference presentations.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

About the Company

Company: Efficient Computer

Headquarters: Austin, TX, USA

Developer of ultra-low-power general-purpose processors using patented technology that can consume up to 100x less energy than comparable ultra-low-power processors. Their programmable platform supports standard high-level languages and AI/ML frameworks to enable long-lived, battery-powered edge devices and energy-efficient SoCs for IoT and edge AI applications.