Applications Engineer - ICV Runset Development

Job Title

Applications Engineer - ICV Runset Development

Role Summary

Develop, validate and qualify physical verification (PV) runsets for IC Validator targeting advanced process nodes. Work with foundries, customers, and field teams to translate PDKs and manufacturing rules into production-ready rule decks and automated qualification workflows.

This role focuses on ensuring first-pass silicon success by delivering robust DRC, LVS, and Fill decks and by resolving verification issues that would otherwise delay tapeout.

Experience Level

Mid-level — typically 5–8 years of hands-on experience in Physical Verification and runset development.

Responsibilities

Core responsibilities include runset development, qualification, automation, debugging, and customer support:

• Develop and validate DRC, LVS, and Fill runsets for IC Validator for advanced nodes (7nm–3nm and beyond).
• Translate foundry PDKs and manufacturing requirements into production-ready rule decks and qualification test cases.
• Automate runset qualification and verification workflows using Perl, Tcl, and Python to reduce manual cycles.
• Debug complex PV failures (LVS topology mismatches, DRC false positives, DFM interactions) that block tapeout.
• Work directly with customers and field application engineers to reproduce issues, define fixes, and deliver solutions under schedule pressure.
• Mentor junior engineers on PV best practices, IC Validator capabilities, and systematic debugging techniques.
• Track competing PV tools and provide technical input to product teams on differentiation and roadmap priorities.

Requirements

Must-have technical skills and experience; items marked as "nice-to-have" are beneficial but not mandatory.

Must have:

• 5–8 years of hands-on experience in Physical Verification focused on DRC, LVS, and Fill runset development.
• Proficiency with IC Validator, Calibre, Pegasus, or PVS and experience writing and debugging complex runsets in at least one tool.
• Strong scripting skills in Perl, Tcl, and Python for automation and qualification.
• Solid understanding of CMOS transistor layout, ASIC design flows, manufacturability, and yield implications.
• Experience working with foundry PDKs and converting process rules into executable verification decks.
• Customer-facing troubleshooting experience and ability to resolve verification blockers under schedule constraints.

Nice to have:

• Exposure to sub-10nm process nodes and advanced node qualification.
• Broad familiarity with competitive EDA tools and the ability to articulate technical tradeoffs between platforms.

Education Requirements

B.Tech, M.Tech, or MS in Electronics, VLSI, or a related engineering discipline (as stated in the posting).

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.