Analog / Mixed-Signal PLL Design Engineer, Senior

Job Title

Analog / Mixed-Signal PLL Design Engineer, Senior

Role Summary

Design analog and mixed-signal integrated circuits for high-speed clocking IP (PLL/DLL/FLL/VCO) intended for SoC and PHY integration across mobile, automotive, IoT and compute products. Work on low-power, low-voltage designs in advanced nanometer CMOS process nodes and collaborate with layout engineers, verification and integration teams to deliver production hard macros.

Experience Level

Senior — typically 5+ years of transistor-level analog/mixed-signal design experience; applicants with equivalent experience meeting the role’s technical requirements will be considered.

Responsibilities

Key responsibilities include architecture, design, verification and delivery of analog/mixed-signal clocking IP and supporting customer integration.

• Architect, design and develop analog/mixed-signal hard macros for high-speed clocking IP.
• Perform custom transistor-level circuit design and run circuit simulations.
• Create behavioural models (e.g., Verilog) and design specifications.
• Work with layout engineers to produce full-custom layouts and ensure analog layout best practices.
• Execute quality assurance, silicon characterization and prepare silicon verification reports.
• Support customer integration, testing and post-silicon debug.

Requirements

Strong technical skills and relevant industry experience. Must-have items listed first.

• Must-have: Minimum ~5 years transistor-level analog/mixed-signal design experience, ideally with frequency synthesis (PLL/VCO) or other high-speed analog IP.
• Hands-on experience with SPICE simulators and schematic-capture tools.
• Design experience with op-amps, bandgaps, differential amplifiers, VCOs and PLL/DLL/FLL architectures.
• Full-custom analog layout skills including extraction, verification and sign-off.
• Scripting experience to automate design and verification tasks.
• Understanding of device physics, power distribution networks and SoC-level mixed-signal integration.
• Familiarity with IC design tool flows and strong written and verbal communication skills.
• Nice-to-have: Experience with high-speed wireline (SerDes), DDR or signal-integrity considerations, and experience in advanced nodes (3nm and beyond).

Education Requirements

Acceptable backgrounds include Bachelor’s, Master’s or PhD in Science, Engineering or a related technical field. The posting specifies options: Bachelor’s + 2+ years relevant ASIC/design experience; Master’s + 1+ year; or PhD. Equivalent practical experience will be considered in lieu of formal degrees.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.