Analog Mixed Signal Modeling Engineer (UL - 02)

Job Title

Analog Mixed Signal Modeling Engineer (UL - 02)

Role Summary

Cirrus Logic's Analog/Mixed-Signal team in Austin seeks an engineer to develop behavioral models and verification infrastructure for mixed-signal IP. The role partners with system architects, analog/digital designers, and verification leads to enable top-down design, AMS/DMS verification, and chip-level integration.

Experience Level

Mid-level. The posting does not specify a required number of years of experience but expects demonstrated experience in mixed-signal product development.

Responsibilities

Key responsibilities include:

• Generate and verify analog circuit equivalent models to support analog design, UVM verification, and hardware/software validation platforms.
• Collaborate with system architects and designers to support architectural exploration of next-generation IP.
• Develop behavioral models using SystemVerilog Real Number Modeling (RNM), user-defined types (UDT), and Verilog-AMS.
• Create DMS and AMS test plans, test benches, and verification methodologies for microarchitectures.
• Support chip-level integration and coordinate design, verification, and modeling feature drop plans.
• Provide primary mixed-signal regression debug support and execute AMS/DMS test platforms and plans.
• Contribute to analog design reviews with recommendations for circuit design and partitioning improvements.
• Work with UVM verification engineers to integrate AMS models into AMS-UVM flows.
• Contribute to automation tools for design, verification, and modeling workflows.

Requirements

Must-have skills and experience:

• Experience in development of mixed-signal products and verification flows.
• Strong background in analog integrated circuit design and ability to interpret circuit schematics.
• Strong background in digital signal processing and control systems.
• Proficiency with SystemVerilog for real number modeling (RNM), test bench development, and verification.
• Proficient in use of AMS simulators.
• Organized, detail-oriented, with strong cross-functional communication and analytical/problem-solving skills.

Nice-to-have / preferred:

• Experience with UVM verification flows, SystemVerilog Assertions or PSL, and formal verification.
• Experience with database/version control systems (Perforce, Git).
• Experience supporting pre-silicon verification and post-silicon validation across teams.
• Working knowledge of Simulink/Simscape and Python scripting.

Education Requirements

Master's degree or higher in Electrical Engineering or Computer Engineering.

About the Company

Company: Cirrus Logic

Headquarters: Austin, TX, United States

Designer and manufacturer of high-precision analog and mixed-signal integrated circuits, specializing in audio and voice processing solutions for consumer electronics and mobile devices, including audio codecs, converters, and SoCs.