Analog/mixed-signal IC Design Engineer - Acacia (Hybrid)

Job Title

Analog/mixed-signal IC Design Engineer - Acacia (Hybrid)

Role Summary

Member of Acacia's Mixed Signal Design team developing high-speed, high-accuracy analog and mixed-signal CMOS ICs for optical transceivers used in data center and telecom networks.

Work in a small IC design group (hybrid, 3 days/week in San Jose) collaborating with digital/DSP, system, package and module teams to take designs from architecture through production.

Experience Level

Senior-level role. See Education Requirements for required years of related experience tied to degree level.

Responsibilities

Primary responsibilities include design ownership, technical leadership, and cross-functional collaboration.

• Architect, design, simulate, lay out, measure and productize ultra-deep sub-micron CMOS analog/mixed-signal blocks for high-speed optical transceivers.
• Lead development of large/complex blocks, track deliverables, and mentor junior engineers.
• Perform peer reviews and establish solid design methodology from conception to production.
• Collaborate with digital/DSP, system, package and hardware teams to meet signal and power-integrity specifications.
• Coordinate with test and lab teams for validation and characterization of ICs.
• Address manufacturability concerns including PVT characterization, EM, self-heating and IR-drop interactions with layout and packaging.

Requirements

Technical must-haves: proven mixed-signal IC design experience and domain expertise in high-speed analog circuits. Education degree requirements are listed separately under Education Requirements.

• Hands-on experience in design, simulation and measurement of high-speed ICs across at least 3 of these areas: high-speed serial links (serdes, ADC/DAC), system link modeling, high-performance output drivers, PLLs, clock transmission/propagation, opamps/PGAs, and equalization techniques.
• Experience with high-speed AMS design practices, verification and silicon bring-up.
• Ability to lead complex designs, provide design reviews, and mentor team members.
• Strong problem-solving skills and ability to work both independently and in a collaborative team environment.

Education Requirements

Minimum qualifications: Bachelor's degree plus 8 years of related experience, or Master's degree plus 6 years of related experience, or PhD plus 3 years of related experience.

Preferred Qualifications

Nice-to-have skills and domain experience that improve fit for the role.

• Experience with electrical transceiver applications (backplane and cable communications).
• Experience with FinFET and GAA process technologies.
• High-frequency layout and floorplanning experience, including power/ground partitioning, analog/digital routing, and passive components (inductors, transformers, transmission lines).
• Design-for-manufacturability experience: PVT characterization, electromigration, self-heating, and IR-drop analysis.
• Laboratory validation experience, including ESD methodology and building test setups.
• Familiarity with design tools and flows: Cadence Virtuoso, Spectre/SpectreX/APS, Virtuoso/Calibre layout validation, EMX, AMS mixed-signal simulation, and MATLAB.

Compensation and Benefits (summary)

Posted U.S. starting salary range: $168,800 to $241,200 (annual). Benefits include medical, dental, vision, 401(k) matching, paid time off, and eligibility for equity awards and bonuses; actual pay varies by location and candidate factors.

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).