Analog/mixed-signal IC Design Engineer - Acacia (Hybrid)
Cisco SystemsJob Title
Analog/mixed-signal IC Design Engineer - Acacia (Hybrid)
Role Summary
Hybrid position (three days per week on-site) based in San Jose, CA. Join Acacia's mixed-signal IC design team to architect, design, layout, measure and productize ultra-deep sub-micron CMOS analog and mixed-signal circuits for high-speed optical transceivers.
This role focuses on high-speed AMS designs for optical communications and requires cross-functional collaboration with digital/DSP, system, package and module teams.
Experience Level
Senior. Minimum experience expectations depend on academic credential: typical hires meet the minimum of ~8+ years relevant experience (or less with advanced degrees as specified in Education Requirements).
Responsibilities
Primary responsibilities include technical leadership of complex analog/mixed-signal blocks and delivering designs from concept through production.
- Architect, design, simulate, and layout high-speed analog/mixed-signal circuits for optical transceivers.
- Lead a large block on complex ICs, mentor engineers, and track deliverables to schedule.
- Perform lab validation and characterize silicon; iterate designs based on measurements.
- Participate in peer design reviews and enforce robust design methodology.
- Collaborate with packaging and hardware teams to meet signal and power integrity targets.
- Contribute to production readiness: PVT characterization, DFM considerations, and reliability analyses.
Requirements
Key technical requirements and preferred skills. Degree and equivalent-experience combinations are listed under Education Requirements and therefore not repeated here.
- Demonstrated experience designing, simulating and measuring high-speed ICs across at least three of the following areas: high-speed serializers/deserializers and data converters; system link modeling; high-performance output drivers; phase-locked loops; clock distribution; opamps/programmable gain amplifiers; equalization techniques.
- Hands-on experience with Cadence Virtuoso and Spectre (including Spectre/APS/SpectreX) for mixed-signal simulation and layout validation tools (Virtuoso, Calibre).
- High-frequency layout experience including floorplanning, power/ground partitioning, analog/digital routing and RF/passive components.
- Experience with lab validation, ESD practices, and construction of test setups for silicon debug.
- Nice-to-have: experience with FinFET/GAA technologies, EM/IR analysis, self-heating characterization, EMX, AMS simulation flows, and MATLAB for data analysis.
Education Requirements
Minimum qualification: Bachelor's degree plus 8 years of related experience, or Master's degree plus 6 years of related experience, or PhD plus 3 years of related experience. The posting allows equivalent related experience in lieu of degree holders as specified above. (No specific field of study was listed in the source.)
About the Company
Company: Cisco Systems
Headquarters: San Jose, CA, United States
Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).
