Analog/Mixed-Signal IC Design Engineer - Acacia
Cisco SystemsJob Title
Analog/Mixed-Signal IC Design Engineer - Acacia
Role Summary
Join the Acacia mixed-signal IC design team to architect, design, layout, measure and productize ultra-deep sub-micron CMOS analog and mixed-signal circuits for high-speed optical transceivers (100G–1.6T+).
The role works closely with digital/DSP, system, package and module teams to deliver integrated transceiver ASIC blocks used in data center and telecom networks. This is a hybrid role with an expected in-office cadence of three days per week in San Jose, CA.
Experience Level
Senior — experience guidance: B.S. + 8 years, M.S. + 6 years, or Ph.D. + 3 years of related industry experience.
Responsibilities
Primary responsibilities include leading a large block on complex mixed-signal chips and driving designs from concept through production.
- Architect, design, simulate, lay out, and verify high-speed analog/mixed-signal IC blocks.
- Lead design efforts for a major block, track deliverables, and mentor junior engineers.
- Participate in peer reviews and enforce solid design methodology and documentation.
- Collaborate with digital/DSP, system, package and module teams to meet system-level signal and power integrity requirements.
- Define and support lab validation, characterization and production bring-up activities.
Requirements
Must-have technical skills and experience. Candidates should meet the minimum experience guidance in the Education Requirements section.
- Proven experience designing, simulating and measuring high-speed ICs; experience must cover at least three of the following areas: high-speed serial links (SERDES, ADC/DAC), system link modeling, high-performance output drivers, phase-locked loops (PLLs), clock transmission/propagation, opamps/PGA, and equalization techniques.
- Deep understanding of signal and power integrity and techniques to meet system specs in mixed-signal ASICs.
- Experience producing silicon from concept to production qualification, including corner/PVT analysis and characterization.
- Strong problem-solving, documentation and cross-functional collaboration skills; ability to lead design reviews and mentor team members.
- Nice-to-have: experience with electrical transceiver applications (backplane/cable), FinFET/GAA process nodes, high-frequency layout and floorplanning, DFM and reliability analyses (EM, self-heating, IR drop), lab validation and ESD practices, and tools such as Cadence Virtuoso, Spectre/APS/SpectreX, Calibre and Matlab.
Education Requirements
Degree and equivalent experience requirement: Bachelors + 8 years related experience, or Masters + 6 years related experience, or PhD + 3 years related experience. No specific field of study was mandated in the posting; equivalent practical experience is acceptable per the degree-equivalent language above.
Additional Information
Role is based in San Jose, CA with a hybrid schedule (approximately three days per week in-office). Compensation ranges were provided for U.S. and Canada locations.
Information on benefits and paid time off was provided by the employer in the original posting.
About the Company
Company: Cisco Systems
Headquarters: San Jose, CA, United States
Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).
