Analog/mixed-signal IC Design Engineer - Acacia

Job Title

Analog/mixed-signal IC Design Engineer - Acacia

Role Summary

Member of the Mixed Signal Design team for Acacia developing high-speed analog/mixed-signal ASICs for optical transceivers (100G–1.6T+). Work covers architecture, design, layout, measurement and productization of ultra-deep-submicron CMOS analog blocks integrated into complex chips.

This is a hybrid role based in the San Jose, CA office (three days per week). Posted US starting salary range: $168,800–$241,200 (base).

Experience Level

Senior level. Position requires substantial IC design experience consistent with the stated minimum qualifications (see Education Requirements for degree/years guidance).

Responsibilities

The role leads design efforts for complex analog/mixed-signal blocks and ensures production-ready deliverables.

• Architect, design, simulate, layout, verify and productize high-speed AMS CMOS blocks.
• Lead a large block on a complex chip, manage deliverables and timelines.
• Mentor and review work of other engineers; participate in peer design reviews.
• Collaborate with digital/DSP, system, package and module teams to meet system-level requirements.
• Ensure signal and power integrity through collaboration with packaging and hardware teams.
• Develop test plans and perform lab measurements and validation of ICs.
• Contribute to design methodology from conception through production and qualification.

Requirements

Key technical skills and experience required or strongly preferred.

• Must-have: Proven experience designing, simulating and measuring high-speed ICs. Demonstrable expertise in at least three areas such as SERDES (serial links, serializers/deserializers, data converters), high-performance output drivers, PLLs, clock transmission/propagation, op amps/programmable gain amplifiers, or equalization techniques.
• Hands-on experience with mixed-signal design and lab validation, including test setup construction and measurement methodology.
• Familiarity with industry tools and flows: Cadence Virtuoso, Spectre/SpectreX/APS, AMS simulators, Virtuoso/Calibre layout validation, EMX, and Matlab.
• High-frequency layout experience and attention to signal/power routing and floorplanning for mixed-signal designs.
• Nice-to-have: Experience with FinFET or GAA technologies, transceiver applications (backplane/cable), design-for-manufacturability (PVT characterization, electromigration, self-heating, IR drop), ESD practices, and RF/passive component layout (inductors, transformers, transmission lines).

Education Requirements

Minimum qualification as stated: Bachelor's degree plus 8 years related experience, Master's degree plus 6 years related experience, or PhD plus 3 years related experience. The posting does not specify required fields of study or mention equivalent-experience language beyond the degree-plus-experience combinations.

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).