Job Title
Analog/mixed-signal IC Design Engineer - Acacia
Role Summary
Member of the Acacia mixed-signal IC design team developing high-speed, high-accuracy analog designs for optical transceivers (100Gβ1.6T+). Work spans architecture, circuit design, layout, measurement and productization of ultra-deep-submicron CMOS ICs.
This is a hybrid role based in San Jose, CA (three days per week onsite) and requires collaboration with digital/DSP, system, packaging and module teams to deliver production-qualified transceiver ASICs.
Experience Level
Senior β role requires substantial industry experience (see Education Requirements for minimum experience by degree).
Responsibilities
Key responsibilities include design leadership for complex mixed-signal blocks, hands-on circuit work, and cross-functional integration.
- Architect, design, layout and validate high-speed analog/mixed-signal circuits and blocks for optical transceivers.
- Lead implementation of a major block on complex chips; own deliverables and schedules.
- Mentor and guide less-experienced engineers; conduct and participate in peer design reviews.
- Develop design methodology from concept through production, including characterization across PVT.
- Collaborate with packaging, hardware, digital/DSP and system teams to meet signal and power integrity targets.
- Support silicon bring-up and lab validation activities, including building test setups and verifying electrical performance.
Requirements
Must-have technical skills and experience. Candidates should meet the minimum qualification and have hands-on experience in multiple listed areas.
- Proven experience designing, simulating and measuring high-speed ICs; practical expertise in at least 3 of the following: high-speed serial links (SERDES/ADCs/DACs), system link modeling, high-performance output drivers, phase-locked loops (PLLs), clock distribution, op amps/programmable gain amplifiers, and equalization techniques.
- Demonstrated ability to take analog/mixed-signal designs from concept to production, including silicon validation and characterization over process, voltage, temperature (PVT).
- Experience ensuring signal and power integrity in mixed-signal ASICs and collaborating with package/hardware teams on floorplanning and routing constraints.
- Strong problem-solving skills, attention to detail, and ability to work independently and in cross-functional teams.
- Excellent communication skills for design reviews and cross-team coordination.
Nice-to-have:
- Experience with FinFET/GAA technologies and high-frequency layout (power/ground planning, analog/digital routing, passives).
- Design-for-manufacturability skills (electromigration, self-heating, IR drop analysis) and ESD practices.
- Familiarity with Cadence Virtuoso, Spectre/APS/SpectreX, Calibre, EMX, AMS mixed-signal simulation flows and Matlab.
Education Requirements
Minimum qualifications: Bachelor's degree plus 8 years of related experience, Master's degree plus 6 years, or PhD plus 3 years of related experience. No specific field-of-study mandated in the posting.
About the Company
Company: Cisco Systems
Headquarters: San Jose, CA, United States
Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).

Date Posted: 2026-06-03