Analog/Mixed-Signal IC Design Engineer - Acacia

Job Title

Analog/Mixed-Signal IC Design Engineer - Acacia

Role Summary

Member of the Acacia Mixed Signal Design team responsible for architecting, designing, laying out, measuring, and productizing high-speed analog/mixed-signal CMOS ICs for optical transceivers. The role works within a small IC design group and collaborates with digital/DSP, system, package, and module teams.

Experience Level

Senior level — position expects extensive industry experience (see Education Requirements for formal experience equivalencies).

Responsibilities

Primary responsibilities include end-to-end analog/mixed-signal IC block delivery, technical leadership, and cross-functional collaboration.

• Architect, design, simulate, layout, and characterize high-speed analog/mixed-signal IC blocks (ultra-deep sub-micron CMOS).
• Lead design efforts for large/complex chip blocks; define deliverables and schedule, and mentor junior engineers.
• Perform circuit simulation, silicon measurement, and debug; iterate designs to meet performance and manufacturability targets.
• Participate in peer design reviews and enforce robust design methodology from concept through production.
• Collaborate with digital/DSP, package, system, and hardware teams to meet signal and power integrity and system-level requirements.
• Support layout floorplanning and high-frequency layout practices to meet performance and manufacturability goals.
• Partner with lab engineers to develop test setups, validate silicon, and support qualification/test activities.

Requirements

Must-have technical experience and skills to perform the role; preferred items listed under "Nice-to-have." (Education degree levels and equivalencies are summarized separately in Education Requirements.)

• Demonstrated experience designing, simulating, and measuring high-speed ICs; experience must include at least three of the following areas: high-speed serial links (SERDES, ADC/DAC), system link modeling, high-performance output drivers, phase-locked loops (PLLs), efficient clock transmission/propagation, opamps/programmable gain amplifiers, or equalization techniques.
• Strong background in high-speed analog/mixed-signal circuit design and verification in CMOS processes.
• Hands-on experience with circuit simulation and mixed-signal tools (examples: Cadence Virtuoso, Spectre/APS/SpectreX, AMS simulations).
• Experience with layout validation tools and flows (Virtuoso layout, Calibre LVS/DRC) and mixed-signal simulation flows.
• Proven ability to lead design blocks, track deliverables, and mentor team members.
• Excellent problem-solving, documentation, and collaboration skills across engineering disciplines.

Nice-to-have

• Experience with electrical transceiver applications (backplane and cable communications).
• Experience with FinFET or GAA process technologies and high-frequency layout, including power/ground planning and high-speed routing.
• Design-for-manufacturability experience: PVT characterization, electromigration, self-heating, IR drop analysis.
• Laboratory validation experience including ESD practices and building test setups.
• Familiarity with EM extraction tools (EMX), Matlab, and other analysis tools.

Education Requirements

Minimum qualification: Bachelor's degree plus 8 years related experience, or Master's degree plus 6 years related experience, or PhD plus 3 years related experience. The posting references "related experience" as acceptable in lieu of additional years of formal education.

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).