Analog, Mixed-Signal & Circuit Design Intern (PhD)
Marvell TechnologyJob Title
Analog, Mixed-Signal & Circuit Design Intern (PhD)
Role Summary
Ph.D. interns are embedded within Marvell's analog design teams to work on transistor-level analog and mixed-signal circuit design tied to active production IP and research-stage silicon. Projects span high-speed SerDes, silicon photonics driver/receiver circuits, ADC/DACs, PLLs, and other precision analog building blocks in advanced CMOS processes.
Interns participate in the full design flow - architecture, schematic, simulation, layout coordination, and silicon bring-up - and present results to engineering teams.
Experience Level
Entry-level internship for currently enrolled Ph.D. candidates; targeted at doctoral students with substantive hands-on analog/mixed-signal design experience.
Responsibilities
Work on transistor-level analog and mixed-signal circuit design across the full production flow and contribute to architecture, verification, and silicon bring-up.
- Design, simulate, and verify analog/mixed-signal circuit blocks from schematic through layout coordination and silicon bring-up.
- Work on production-grade IP: high-speed SerDes building blocks, silicon photonics drivers/receivers, ADC/DAC architectures, PLLs, clock distribution, LDOs, and precision analog blocks.
- Use Cadence tools and system-level tools (MATLAB/Python) for design, simulation, and verification.
- Collaborate with layout engineers on layout-aware design, parasitic extraction, and post-layout iteration.
- Participate in design reviews and present technical results and trade-offs to the engineering team.
- Follow a structured analog design curriculum alongside other Ph.D. interns.
Requirements
Must-have technical skills and practical experience required for successful contribution.
- Hands-on experience designing and simulating transistor-level analog/mixed-signal circuits (e.g., PLLs, SerDes building blocks, ADCs/DACs, amplifiers, LDOs, high-speed I/O).
- Strong fundamentals in device physics, noise analysis, linearity, stability, and low-power techniques in advanced CMOS processes.
- Proven ability to simulate and verify designs independently using industry-standard tools such as Cadence Virtuoso and Spectre.
- Ability to communicate design decisions and defend engineering trade-offs in design reviews and presentations.
Nice-to-have / Preferred:
- Experience with FinFET process nodes (7nm, 5nm, 3nm or equivalent).
- Familiarity with high-speed serial link architectures, optical transceiver circuits, or die-to-die interconnects.
- Exposure to layout-aware design, parasitic extraction, and post-layout simulation.
- Experience with MATLAB or Python for system-level modeling and behavioral modeling in Verilog-A.
Education Requirements
Currently enrolled in a Ph.D. program in Electrical Engineering or a closely related field with a research focus in analog, mixed-signal, or RF circuit design (Ph.D. enrollment is required for this internship).
About the Company
Company: Marvell Technology
Headquarters: Santa Clara, California, United States
Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.
