Analog / Mixed-Signal Circuit Design Engineer

Job Title

Analog / Mixed-Signal Circuit Design Engineer

Role Summary

Design and verify transistor-level analog and mixed-signal IP blocks for advanced CMOS process nodes and support silicon bring-up and characterization. Work closely with layout, SoC integration, test, and foundry teams to deliver robust first-pass silicon.

Role covers architecture, SPICE-level simulation and verification, documentation, and mentorship within an IC design team focused on power, clocking, high-speed SERDES, and analog infrastructure.

Experience Level

Mid-level - minimum 3 years of professional experience in analog/mixed-signal IC circuit design.

Responsibilities

Deliver and validate analog/mixed-signal circuit IP across the full development cycle.

• Transistor-level design of analog/mixed-signal macros for advanced nodes (28nm, 16nm FinFET, 7nm and below).
• Architect and implement LDOs, bandgap references, PORs, bias networks, and protection circuits (UV/OV, brown-out, soft-start).
• Design high-speed RX front-ends, CDR, DLL/PLL, and TX drivers with programmable swing, pre-emphasis, and equalization for PCIe/USB/MIPI/DDR/SerDes interfaces.
• Design DC-DC switching converters, charge pumps, analog switches, oscillators, and clock distribution networks meeting noise, jitter, and EMI targets.
• Perform comprehensive SPICE-level simulations (DC/AC/transient/noise/Monte Carlo/PVT) and post-layout simulations with extracted parasitics to validate schematic vs. silicon performance.
• Develop Verilog-A/Verilog-AMS behavioral models for mixed-signal co-simulation and maintain regression test benches.
• Author specifications, schematic documentation, simulation reports, and participate in design and architectural reviews.
• Support silicon bring-up, characterization, root-cause analysis, and propose design fixes; collaborate on ATE test development.
• Collaborate with layout, DFT, and SoC teams; mentor junior designers and engage with foundries and PDK/device model reviews.

Requirements

Must-have technical skills and practical experience; preferred items listed separately.

• Must: Minimum 3 years professional experience in analog/mixed-signal IC circuit design.
• Must: Proficiency with Cadence Virtuoso schematic editor and ADE (ADE-L/XL/GXL).
• Must: Hands-on SPICE simulation experience (Cadence Spectre, HSPICE, or Eldo) including Monte Carlo and PVT corner analysis; post-layout simulation with parasitics.
• Must: Demonstrated design experience across multiple macro categories (power management, clocking, high-speed interfaces, references, or similar).
• Must: Strong understanding of MOSFET device physics, noise analysis, stability/phase margin, mismatch and variation effects.
• Must: Knowledge of analog design fundamentals: op-amp topologies, feedback, frequency compensation, and bandgap references.
• Preferred: Verilog-A / Verilog-AMS behavioral modeling experience for mixed-signal simulation.
• Preferred: Experience with high-speed serial standards (PCIe Gen4/5, USB3.x/4, DDR5, MIPI, or custom SerDes at ~10–12 Gbps) and foundry collaboration (TSMC, Samsung, GlobalFoundries, Intel Foundry).

Education Requirements

Bachelor of Science in Electrical Engineering (B.S./BSEE) required.

About the Company

Company: Silicon Dreams

Headquarters: Thoothukudi, Tamil Nadu, India

Silicon Dreams is an engineering services and semiconductor design firm specializing in analog and mixed-signal integrated circuit design, IP development, and silicon bring-up for advanced CMOS nodes and high-speed serial interfaces.