Analog Layout Staff Engineer

Job Title

Analog Layout Staff Engineer

Role Summary

Lead layout engineer responsible for full-custom analog/mixed-signal layout of high-speed SerDes IPs and other complex analog blocks across advanced process nodes. Work within a small, cross-functional Central Engineering AMS team to take designs from floorplanning through tape-out.

Experience Level

Senior — typically 6–10 years of experience in high-speed analog/custom layout development.

Responsibilities

The primary responsibilities center on designing, verifying, and delivering high-performance analog layouts and improving layout processes.

• Lead layout development for high-speed SerDes IPs and analog blocks (ADC, PLL, bandgap, LDO) in advanced FinFET and emerging nodes.
• Translate schematics into optimized floorplans and full-custom layouts; drive ownership from layout through tape-out.
• Perform RC extraction and physical verification closure (DRC, LVS, ERC, DFM); resolve antenna, IR drop, and electromigration issues.
• Lead layout reviews, mentor junior engineers, and promote best practices and design-rule compliance.
• Collaborate with global circuit designers and cross-functional teams to meet performance and schedule targets.
• Develop and maintain automation scripts to improve productivity and layout consistency.

Requirements

Must-have technical skills, experience, and work practices required to perform the role.

• 6–10 years of hands-on experience in high-speed analog/custom layout development.
• Proven experience in full-custom layout and verification, including RC extraction and physical verification workflows (DRC, LVS, ERC, DFM) and EMIR analysis.
• Hands-on expertise with mixed-signal/analog/high-speed layouts (SerDes, ADC/DAC, PLL) in advanced FinFET technologies.
• Proficiency with Cadence Virtuoso and industry-standard EDA tools.
• Strong understanding of semiconductor process technologies, device physics, matching, shielding, clock routing, power planning, ESD, and latch-up mitigation.
• Ability to own the full development cycle from floorplanning to delivery and to communicate effectively with global teams.
• May require eligibility to access export-controlled technology; candidates may be subject to export license review prior to employment.

Nice-to-have:

• Scripting skills for automation (Perl, Tcl, SKILL).
• Experience with emerging nodes (GAA) or advanced process transitions.
• Prior experience mentoring or leading small layout teams.

Education Requirements

BE / B.Tech or MS / M.Tech in Electrical/Electronics Engineering, Microelectronics, or a closely related field is specified.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.