Analog Layout Staff Engineer

Job Title

Analog Layout Staff Engineer

Role Summary

Develop and deliver full-custom analog/mixed-signal layouts for high-speed SerDes IPs and other analog blocks across advanced FinFET and emerging nodes. Own floorplanning, layout implementation, verification closure, and tape-out readiness while collaborating with circuit designers and cross-functional teams.

Contribute technical leadership within a small AMS layout team: drive layout quality, mentor junior engineers, and create automation to improve productivity and design consistency.

Experience Level

Senior — 6–10 years of experience in high-speed analog/custom layout development.

Responsibilities

The role requires end-to-end ownership of analog/mixed-signal layout tasks and leadership in layout execution and verification.

• Lead layout development for high-speed SerDes IPs and analog blocks (ADCs, PLLs, bandgaps, LDOs) in advanced process nodes.
• Translate schematics into optimized layouts; perform floorplanning and implement physical design constraints.
• Execute physical verification closure: resolve DRC, LVS, ERC, antenna violations and DFM issues.
• Perform RC extraction and EMIR analysis; implement fixes for IR drop and electromigration.
• Lead layout reviews and coordinate with circuit, verification, and tape-out teams to meet schedules.
• Mentor junior layout engineers and promote best practices for matching, shielding, routing, and power planning.
• Develop and maintain automation/scripts to improve layout productivity and consistency.

Requirements

Must-have technical skills and experience for successful performance in this role.

• Strong understanding of semiconductor process technologies, device physics, and layout effects in advanced nodes.
• Proven experience in full-custom circuit layout and verification, including RC extraction and physical verification (DRC, LVS, ERC, DFM).
• Hands-on expertise in mixed-signal/analog/high-speed layouts (SerDes, ADC/DAC, PLL) on FinFET technologies.
• Proficiency with Cadence Virtuoso and industry-standard EDA tools; ability to work with layout/verification flows.
• Knowledge of critical layout techniques: matching, shielding, clock routing, power planning, ESD, and latch-up mitigation.
• Ability to own the full development cycle from floorplanning to delivery, and to communicate status clearly with global teams.
• Self-motivated, adaptable, and able to work in a fast-paced engineering environment.

Nice-to-have:

• Scripting experience for automation (Perl, Tcl, SKILL).
• Experience with EMIR analysis automation and advanced DFM/DFY flows.

Education Requirements

BE/B.Tech or MS/M.Tech in Electrical/Electronics Engineering, Microelectronics, or a related field. The posting specifies 6–10 years of relevant high-speed analog/custom layout experience.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.