Analog Layout Senior Engineer

Job Title

Analog Layout Senior Engineer

Role Summary

Responsible for full-custom layout of high-speed SerDes IPs and complex analog/mixed-signal blocks within Marvell's Central Engineering AMS team. Translate schematics into manufacturable layouts across advanced FinFET and emerging nodes and drive designs from floorplanning through tape-out.

Small, agile team working on analog layout for AI, cloud, storage, security, and networking products.

Experience Level

Senior; posting specifies 2–5 years of relevant high-speed analog/custom layout experience.

Responsibilities

Key responsibilities include:

• Lead layout of high-speed SerDes IPs and analog blocks (ADCs, PLLs, bandgaps, LDOs) in deep sub-micron CMOS, FinFET, and GAA nodes.
• Translate schematics into optimized, manufacturable full-custom layouts and own end-to-end delivery from floorplanning to tape-out.
• Perform physical verification closure and RC extraction; resolve DRC, LVS, ERC, antenna issues and address IR drop/electromigration (EMIR) concerns.
• Collaborate with circuit designers and cross-functional teams to meet performance and manufacturability targets.
• Lead layout reviews, mentor junior engineers, and promote best practices for matching, shielding, routing, and power planning.
• Develop automation and productivity scripts (Perl, Tcl, SKILL) and improve layout tooling and processes.

Requirements

Must-have skills and experience:

• Proven experience in full-custom analog/mixed-signal layout and verification, including RC extraction and physical verification (DRC/LVS/ERC/DFM).
• Hands-on experience with mixed-signal/high-speed layouts (SerDes, ADC/DAC, PLL) at advanced FinFET nodes.
• Proficiency with Cadence Virtuoso and industry-standard EDA tools.
• Strong understanding of semiconductor process technologies, device physics, and layout effects in advanced nodes.
• Knowledge of layout techniques: matching, shielding, clock routing, power planning, ESD and latch-up mitigation.
• Ability to own full development cycle and communicate effectively with global teams.

Nice-to-have:

• Scripting for automation (Perl, Tcl, SKILL).
• Experience performing EMIR analysis and implementing fixes.

Education Requirements

BE/B.Tech or MS/M.Tech in Electrical/Electronics Engineering, Microelectronics, or related fields (as stated in the posting).

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.