Analog Layout Principal Engineer

Job Title

Analog Layout Principal Engineer

Role Summary

Senior-layout engineer responsible for independent delivery of complex analog, mixed-signal and custom layouts from floorplanning to tapeout. Member of Central Engineering providing layout IP and integration for multiple product groups.

Experience Level

Senior - typically 15+ years of relevant analog/mixed-signal and custom layout engineering experience.

Responsibilities

Key responsibilities include ownership of layout deliverables, physical closure, and cross-team coordination.

• Design and develop complex analog, mixed-signal and custom layouts using Cadence Virtuoso and similar EDA tools across advanced nodes (deep sub-micron, FinFET, GAA).
• Drive physical verification and closure; resolve DRC, LVS, ERC and antenna violations within project schedules.
• Define layout architecture: shielding, isolation, EM/IR optimization, parasitic management, device matching, and robust power routing.
• Own layout planning from floorplanning through final tapeout and support tapeout activities under aggressive schedules.
• Coordinate with design, verification, package and physical implementation teams; act as principal interface between layout and design teams.
• Lead technical discussions and layout reviews; mentor team members and coordinate multiple macro owners to drive convergence.
• Provide layout feedback that influences circuit quality, performance and architecture; stay current with semiconductor process and tool developments.

Requirements

Essential technical skills and experience required for immediate impact.

• Extensive hands-on experience delivering high-speed and precision analog layouts across multiple process technologies and nodes.
• Expert proficiency with EDA layout tools and flows, especially Cadence Virtuoso; ability to influence layout methodologies.
• Proven track record of end-to-end ownership of complex, critical IPs and successful tapeouts.
• Deep practical knowledge of EM/IR, latch-up prevention, ESD protection, antenna effects, and reliability considerations.
• Strong skills in parasitic minimization, clock routing, shielding, biasing and signal flow optimization.
• Ability to lead cross-functional teams, present to global stakeholders, and drive technical decisions.
• Effective communication, collaboration, and mentoring abilities.
• Experience working with advanced nodes (deep sub-micron, FinFET, GAA) and managing layout for performance-critical designs.
• Nice-to-have: prior experience coordinating large teams or multiple macro owners across projects.

Education Requirements

Bachelor's or master's degree (BE/B.Tech or MS/M.Tech) in Electronics & Communication, Electrical & Electronics, or a related field from a reputed institution. (Degrees specified in source.)

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.