Analog Layout Lead

Job Title

Analog Layout Lead

Role Summary

Lead full-custom analog and mixed-signal layout efforts for next-generation silicon platforms. Work closely with circuit design, physical design, process technology, and PDK teams to deliver manufacturable layouts that meet performance, noise, matching, and signal-integrity targets across advanced CMOS nodes.

Experience Level

Senior level. Requires substantial hands-on experience; posting requests 8+ years of relevant layout experience.

Responsibilities

Primary responsibilities for this role include technical leadership, rigorous physical implementation, and cross-team coordination to achieve tape-out readiness.

• Lead full-custom layout of analog and mixed-signal blocks (PLLs, ADCs, DACs, LDOs, bandgaps, high-speed I/O) from concept to tape-out.
• Define and enforce analog layout methodologies, design rules, matching, shielding, and noise-isolation best practices.
• Drive parasitic-aware layout strategies and iterate on layout-versus-schematic and post-layout simulations to meet performance targets.
• Own physical verification closure (DRC, LVS, antenna checks) and sign-off readiness across advanced process nodes.
• Establish floorplanning and integration strategies for analog IP inside mixed-signal SoCs.
• Provide technical guidance, review layouts, and manage quality and schedule across internal engineers and external contractors.
• Partner with process and PDK teams to evaluate new nodes and resolve layout-induced performance issues.
• Develop long-term physical design roadmaps and methodology investments that scale across multiple silicon programs.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• Must-have: 8+ years of experience in full-custom analog and mixed-signal layout for production silicon in advanced CMOS nodes (preferably 28nm or below).
• Must-have: 8+ years hands-on with industry-standard layout tools such as Cadence Virtuoso for schematic-driven layout, parasitic extraction, and physical verification.
• Must-have: Proven experience leading layout of high-performance analog blocks (PLLs, voltage regulators, data converters, high-speed interfaces) through tape-out.
• Must-have: Experience defining and implementing layout methodologies for matching, shielding, noise isolation, and signal integrity in mixed-signal environments.
• Must-have: Experience collaborating with circuit designers to translate simulation requirements into layout constraints and verification closure.
• Must-have: Experience managing, mentoring, and reviewing layout engineers and coordinating deliverables with contractors.
• Nice-to-have: Familiarity with post-layout simulation flows (RC extraction, back-annotation) and tools such as Spectre or Calibre.
• Nice-to-have: Experience with PDK evaluation, design rule documentation, photonics-related analog layout, 3D stacking or advanced packaging layout considerations, or reusable analog layout templates.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field, or equivalent practical experience.

About the Company

Company: Lumilens

Headquarters: San Jose, CA, USA

Lumilens develops integrated photonics and optical interconnect solutions for high-speed data communication and chip-to-chip interfaces, focusing on optical front-end hardware and co-packaged optics for advanced semiconductor systems.