Analog Layout Intern
Marvell TechnologyJob Title
Analog Layout Intern
Role Summary
Join Marvell's Central Engineering analog layout team as an intern focused on translating analog IC schematics into manufacturable physical layouts and supporting real tapeouts across advanced process nodes. You will work on a small, global team and contribute to semiconductor IP used across multiple product lines.
This role may require eligibility to access export-controlled technology; non-U.S. citizens may be subject to export license review before employment.
Experience Level
Entry-level (Internship). Intended for current undergraduate students; no prior full-time industry experience required.
Responsibilities
Primary responsibilities include converting schematic designs into layout, running verification checks, and collaborating with designers to meet specifications.
- Translate analog schematics into physical layout using Cadence Virtuoso and related EDA tools.
- Perform physical verification flows such as DRC and LVS and resolve layout issues.
- Work with Analog IC Designers to debug and iterate layouts to meet electrical and manufacturability targets.
- Present progress and technical findings in team meetings and project reviews.
- Contribute to development of semiconductor IP across advanced process nodes (e.g., FinFET, 3nm/2nm-class technologies).
Requirements
Must-have technical skills and professional capabilities.
- Fundamental understanding of analog circuit concepts and microelectronics.
- Familiarity with physical IC design tools (Cadence Virtuoso, Calibre, or similar).
- Ability to run and interpret results from physical verification flows (DRC/LVS) and debug layout issues.
- Strong verbal and written communication skills; able to present technical updates to global teams. Fluency in English required.
- Ability to work independently and manage multiple tasks concurrently.
Nice-to-have / preferred:
- Hands-on experience with ERC/antenna checks and other verification flows.
- Exposure to advanced process nodes and analog/mixed-signal layout techniques.
- Scripting experience for layout automation (SKILL, Python, Tcl).
Education Requirements
Currently pursuing a Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field with an expected graduation between Fall 2027 and Summer 2028. Relevant coursework or hands-on experience in analog design, IC layout, or VLSI design is expected. (Additional compensation may be available for PhD intern candidates.)
About the Company
Company: Marvell Technology
Headquarters: Santa Clara, California, United States
Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.
