Analog Layout Design Engineer

Job Title

Analog Layout Design Engineer

Role Summary

Design and verify complex analog IC layouts to meet electrical, performance, and reliability specifications. Work on floorplanning, power grid, ESD/bump planning, and detailed signal routing for analog blocks while driving layout methodology and automation improvements.

Collaborate with analog circuit designers, process technology, and package teams; troubleshoot layout, tool, and flow issues; and provide technical leadership for small layout teams on larger blocks.

Experience Level

Mid-level. The posting requests approximately 6+ years of relevant layout experience.

Responsibilities

Key responsibilities include:

• Develop and implement complex analog layouts (RX, TX, LDOs, ADC/DAC blocks, PLLs, amplifiers, charge pumps, current mirrors, etc.).
• Perform full layout verification: design-rule checks, electrical verification (EM/IR), ESD checks, extraction and LVS where required.
• Plan micro-floorplans, shielding and matching for critical signals to meet performance, area, and power targets.
• Design and analyze power grids, ESD structures, and bump placement.
• Create execution plans, estimate effort, assign and track work for small teams; act as a technical lead while contributing individually.
• Develop and drive layout automation, flows, and methodology improvements to increase productivity and quality.
• Collaborate with circuit, process, and package teams to resolve tradeoffs and meet specifications.
• Troubleshoot layout and tool/flow/methodology issues.

Requirements

Must-have technical skills and experience:

• Approximately 6+ years of analog layout experience (as stated in posting).
• Expertise with layout and verification tools such as Cadence Virtuoso/Custom Compiler, ICV/Calibre, RedHawk/Voltus, and extraction tools like StarRC.
• Strong understanding of analog layout practices including matching, routing for critical signals, and ESD-related layout techniques.
• Familiarity with design rule decks and process-related constraints.
• Experience with complex analog circuit types: ADCs, DACs, regulators, PLLs, amplifiers, charge pumps, current mirrors, etc.
• Demonstrated ability to estimate effort, plan execution, and lead or coordinate a small team of layout designers.
• Interest in and experience implementing layout automation or productivity improvements.

Education Requirements

Minimum educational qualification: Bachelor's or Master's degree in Electrical Engineering (B.E./B.Tech or M.E./M.Tech in EE). (Source lists Master or Bachelors in EE.)

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.