Analog IC Design and Verification Engineer

Job Title

Analog IC Design and Verification Engineer

Role Summary

Design and verify analog and mixed-signal integrated circuits for neural-interface system-on-chip (SoC) products within the Brain Interfaces SoC Department. The role covers transistor-level circuit design, block-level layout coordination, analog verification, and silicon validation.

Work with cross-functional teams including layout engineers, lab test engineers, and external vendors to deliver production-ready analog IP and chips.

Experience Level

Mid-level — typically requires 5+ years of relevant industry experience in analog/mixed-signal IC design and silicon validation.

Responsibilities

Primary responsibilities include designing, verifying, and validating analog/mixed-signal blocks and subsystems for SoC integration.

• Design transistor-level analog circuit building blocks and subsystems to meet noise, mismatch, distortion, power, and cost targets.
• Oversee and coordinate block-level layout with layout teams.
• Plan and execute analog verification for IP or chip portions; run complex simulations and analyses (power, performance, linearity, yield).
• Develop, program, and run lab and simulation tests; analyze results and ensure issues are resolved.
• Review and mentor junior engineers' tests and analyses.
• Consult with internal stakeholders and third-party vendors to align implementations with system requirements.

Requirements

Must-have technical experience and skills. Preferred items are listed where applicable.

• Minimum 5 years of experience in analog/mixed-signal CMOS integrated circuit design with a demonstrated track record of silicon validation.
• Experience designing specific analog blocks (e.g., ADCs, DACs, VCO/PLL, CODEC, high-speed PHY/SerDes) at transistor level.
• Proven ability to plan and execute analog verification and run complex simulations (power, linearity, yield).
• Experience working with layout teams and overseeing block-level layout implementation.
• Experience designing and executing lab tests, and analyzing high-precision analog/mixed-signal measurements.
• Ability to mentor or review work from junior engineers and contribute to team processes.
• Strong analytical problem-solving skills and practical engineering judgment.

Nice-to-have:

• Functional modeling and logic verification experience (Verilog-AMS, SystemVerilog).
• Experience with advanced CMOS FinFET technologies and design-for-high-volume production.
• Scripting and automation skills for simulation and test flow.

Education Requirements

Requires a Bachelor of Science (BS) with at least 5 years of related experience after the BS. Preferred: Master's or PhD in electrical engineering, physics, or a related technical field. (Source also highlights domain-specific experience rather than certifications.)

About the Company

Company: Neuralink

Headquarters: Fremont, California, United States

Neuralink is a technology company developing devices for a bidirectional interface with the brain, aiming to restore movement to paralyzed individuals and revolutionize human interaction with the digital world. The company focuses on advanced chip architecture and silicon implementation for high-bandwidth brain-computer interfaces, fostering a collaborative environment for engineers dedicated to pushing the boundaries of innovation.