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Analog I/O Senior Design Engineer

Synopsys
September 02, 2026
Full-time
On-site
Noida, Uttar Pradesh, India
Semiconductor IP Jobs, Level - Senior

Job Title

Analog I/O Senior Design Engineer

Role Summary

Design and qualify robust ESD and Latch‑Up (LU) protection and I/O circuitry for high‑performance interface IP targeting advanced processes (FinFET, FDSOI, BCD). The role owns projects from schematic and simulation through layout, silicon qualification and production release, and works closely with foundries and cross‑functional teams.

Experience Level

Senior — senior-level role (title indicates senior level). No explicit years-of-experience stated.

Responsibilities

Primary responsibilities include hands-on analog I/O and protection design, verification, and qualification.

  • Design and develop ESD and Latch‑Up robust solutions for interface IPs in FinFET, FDSOI, and BCD processes.
  • Own full lifecycle of ESD structures: schematic, simulation, layout, silicon qualification, and production release.
  • Lead I/O ring design, review, and optimization for performance and robustness.
  • Develop and qualify interface testchips to validate ESD and LU performance against customer requirements.
  • Perform ESD simulations by constructing detailed ESD networks and executing advanced analyses.
  • Apply foundry PERC rules and use PERC check tools to validate design compliance.
  • Collaborate with foundries, layout, and design teams to integrate and deliver solutions on schedule.

Requirements

Required technical skills and proven experience for immediate contribution.

  • Proven experience in analog circuit design with focus on I/O development and ESD/LU robustness.
  • Hands-on experience with FinFET, FDSOI, and BCD process technologies from major foundries.
  • Strong background in ESD and Latch‑Up qualification methodologies, including testchip development and validation.
  • Proficiency in ESD simulation, ESD network construction, and industry-standard ESD tools.
  • Practical experience applying PERC rules and using PERC verification tools.
  • Experience with silicon qualification activities and production release processes.
  • Effective collaborator across foundry, design, and layout teams and able to communicate technical results clearly.
  • Nice-to-have: mentoring experience and prior work on interface IP delivered to customers.

Education Requirements

Not specified.


About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.

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Date Posted: 2026-08-31