Analog Digital Mask Design Engineer

Job Title

Analog Digital Mask Design Engineer

Role Summary

This role delivers full-custom and digital/analog mixed-signal IC layouts and mask-level assemblies for high-performance CMOS processes. You will work within the Circuit Solutions Group on digital-heavy IPs that include analog blocks, collaborating with design, verification and manufacturing teams.

Experience Level

Mid-level — requires approximately 3+ years of relevant analog layout experience.

Responsibilities

Primary responsibilities include producing, verifying and optimizing IC layouts for advanced process nodes.

• Execute IC layout for high-performance CMOS integrated circuits at advanced nodes (2nm–7nm and below).
• Deliver layouts for digital+analog IPs, including significant digital components and analog blocks.
• Perform full-custom layout of analog/mixed-signal blocks (op-amps, bandgaps, PLLs, ADCs, DACs, LDOs, voltage regulators).
• Adopt and apply best layout practices and methodology for composing analog and digital layouts.
• Ensure design quality by meeting matching, symmetry and parasitic-sensitivity requirements.
• Execute layout verification (DRC, LVS, ERC, antenna checks, EMIR) and resolve violations.
• Optimize layouts for area, performance and manufacturability.
• Perform floorplanning, block-level routing and macro-level assembly.

Requirements

Must-have technical skills and demonstrable experience. Education and degree expectations are in the Education Requirements section below.

• Minimum ~3 years of hands-on analog layout experience in advanced CMOS processes.
• Proven experience laying out high-performance analog blocks such as current mirrors, sense amps and bandgaps for production silicon.
• Strong working knowledge of industry-standard EDA tools (Cadence toolset).
• Practical knowledge of analog layout guidelines: matching, common-centroid placement, symmetry, signal shielding, dummy devices, thermal-aware layout and electromigration considerations.
• Experience performing and debugging DRC/LVS/EMIR/antenna issues.
• Ability to work independently, define schedules and meet delivery targets.
• Nice-to-have: background in sub-micron/FinFET nodes (7nm and below), experience with distributed design teams, and high-speed I/O layout experience.

Education Requirements

BE/B.Tech or M.Tech in Electrical & Electronics or equivalent practical experience; the posting explicitly allows equivalent experience in lieu of the listed degrees.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.