Analog Design Staff Engineer

Job Title

Analog Design Staff Engineer

Role Summary

Senior analog design engineer responsible for architecting, designing, verifying, and bringing up high-speed SerDes analog blocks for production IP. The role works closely with layout, digital RTL, verification, and characterization teams to deliver multi-gigabit transceivers for AI accelerators, data center, automotive, and consumer SoCs.

Experience Level

Senior. Typical expectation is 5+ years of relevant high-speed analog/SerDes design experience; more senior technical scope and ownership is expected. (See Education Requirements for degree-specific guidance.)

Responsibilities

Design and deliver analog/mixed-signal SerDes building blocks and support their lifecycle from spec to silicon.

• Design and optimize analog front-end blocks: drivers, equalizers (CTLE, FFE, DFE), CDRs, PLLs/DLLs/VCOs, phase interpolators, bandgaps, and regulators.
• Run SPICE simulations across PVT corners, create verification testbenches, and validate performance against protocol specs.
• Collaborate with layout engineers to minimize parasitics, mismatch, and proximity effects; drive post-layout verification.
• Coordinate with digital RTL teams on calibration loops, adaptation algorithms, and control logic for real-time tuning.
• Present simulation results, design tradeoffs, and performance data in peer reviews and customer technical meetings.
• Document circuit architecture, verification strategies, and test plans; support characterization and bring-up activities.
• Perform design-for-reliability checks for electromigration, IR drop, aging, and ESD.

Requirements

Must-have technical skills and proven track record.

• Silicon-proven experience designing and bringing up analog or mixed-signal blocks in production chips.
• Deep hands-on expertise in multiple SerDes building blocks (analog front ends, drivers, PLLs/CDRs, equalizers, phase interpolators, etc.).
• Strong proficiency with SPICE simulation workflows and sub-micron CMOS design methodologies; able to set up corners, sweeps, and interpret key metrics.
• Experience optimizing layout for performance, including parasitic extraction, device matching, and reliability considerations.
• Proven ability to work cross-functionally with layout, digital, and characterization teams and to communicate technical results clearly.
• Nice-to-have: scripting experience (TCL, Perl) for automation and simulation flow setup.
• Nice-to-have: working knowledge of high-speed serial standards (PAM4, PCIe, Ethernet, USB, HDMI, MIPI, SATA).

Education Requirements

PhD with 2+ years of hands-on SerDes or high-speed analog design experience, or BTech/MTech with 5–10 years in the same domain. The posting does not specify a required field of study beyond domain experience in high-speed analog/SerDes design.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.