Analog Design Staff Engineer

Job Title

Analog Design Staff Engineer

Role Summary

Senior analog/mixed-signal transistor-level design engineer for high-speed SerDes PHY IP. Work with the Yerevan Cross-Functional Ultra-High-Speed R&D team to design, simulate, model, and review circuits that meet performance, power, jitter, and reliability targets for production silicon.

Experience Level

Senior. The posting specifies 4+ years of hands-on analog and mixed-signal IC design experience; the title indicates staff-level responsibility.

Responsibilities

Primary responsibilities include circuit design, verification, modeling, and cross-discipline coordination to deliver robust SerDes PHY IP.

• Design and verify transistor-level analog and mixed-signal circuits (transmitters, receivers, PLLs/DLLs, VCOs, equalizers, samplers, bias/reference circuits).
• Develop circuit architectures and perform tradeoff analysis across performance, power, noise, jitter, and reliability.
• Run DC, AC, transient, cross-corner PVT, aging, EMIR/SHE, and Monte Carlo simulations to validate robustness.
• Build and validate circuit simulation models and Verilog-A behavioral models for IP integration and system-level validation.
• Review custom layout implementations and work with layout engineers to ensure post-layout performance meets specifications.
• Prepare technical documentation, lead design reviews, and present tradeoff decisions to cross-functional teams.
• Mentor junior engineers and provide technical guidance on design, simulation methodology, and debugging.

Requirements

Must-have technical skills and relevant experience. Nice-to-have items noted.

• Must-have: 4+ years of hands-on analog and mixed-signal IC design in advanced CMOS technology nodes.
• Must-have: Deep expertise in transistor-level design, custom IC design flow, and layout effects (parasitics, matching, proximity).
• Must-have: Proven track record designing and verifying high-speed components (transmitters, receivers, PLLs/DLLs, VCOs, equalizers, samplers, reference circuits) for SerDes or similar applications.
• Must-have: Strong simulation skills across DC/AC/Transient, cross-corner PVT, aging, EMIR/SHE, and Monte Carlo analyses.
• Must-have: Experience developing circuit simulation models and Verilog-A behavioral models.
• Must-have: Proficiency with scripting (TCL, Python, Perl, MATLAB, or C).
• Must-have: Ability to investigate post-layout vs schematic mismatches via netlists and extraction decks; strong cross-team communication.
• Nice-to-have: Experience with AI tools for design automation.
• Language: Fluent English for technical presentations and collaboration.

Education Requirements

BS or MS in Electrical Engineering or Electronics Engineering.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.