Analog Design Senior Staff Engineer

Job Title

Analog Design Senior Staff Engineer

Role Summary

Design, develop, and validate multi-Gbps NRZ and PAM4 SerDes analog IP as part of an analog and mixed-signal R&D team. Work from standards and block specifications through architecture, circuit design, layout oversight, simulation correlation and silicon validation with cross-functional analog, digital and hardware teams.

Experience Level

Senior — requires significant experience; the posting specifies 6+ years of SerDes/high-speed analog design experience.

Responsibilities

Deliver high-speed SerDes analog building blocks and ensure silicon-quality results across the full design flow.

• Develop calibration and adaptation algorithms for transceivers to optimize performance.
• Propose and refine circuit implementations to meet power, area, and performance targets.
• Develop and maintain SerDes system models (MATLAB/Simulink) for PAM4 transceivers targeting PCIe and Ethernet standards.
• Own analog macro-level design and derive analog specifications from standards and architecture documents.
• Oversee physical layout to minimize parasitics, device stress, and variation effects.
• Correlate simulated performance with silicon measurements and drive design fixes.
• Collaborate with analog, digital, and hardware engineers throughout development and post-silicon validation.
• Contribute to lab testing, measurement analysis, and system-level validation of high-speed links.

Requirements

Key technical skills and experience required; items labeled as "Nice-to-have" are desirable but not mandatory.

• Must-have: 6+ years of SerDes/high-speed analog circuit design experience.
• Must-have: Silicon-proven experience implementing TX, RX and clock-path circuits within SerDes designs.
• Must-have: Strong experience modeling circuits and systems in MATLAB/Simulink.
• Must-have: Solid understanding of DSP and communications theory, including equalization, encoding, and noise/crosstalk mitigation.
• Must-have: Proficiency analyzing link budgets for PAM4 high-speed serial links.
• Must-have: Experience with wireline protocols (PCIe, Ethernet, JESD204C, CPRI) and familiarity with optical protocols referenced.
• Must-have: Detailed design experience with SerDes sub-circuits such as receive equalizers, data samplers, V/I-mode drivers, serializers/deserializers, VCOs, phase interpolators, DLL/PLL, bandgap references, ADCs, DACs.
• Must-have: Experience optimizing FinFET CMOS layout to reduce parasitic effects and device mismatch.
• Must-have: Proficiency with SPICE simulators and simulation methodologies.
• Must-have: Knowledge of Verilog-A for analog behavioral modeling and simulation control/data capture.
• Nice-to-have: Demonstrated mentoring, documentation, and presentation skills; experience working in multidisciplinary teams.

Education Requirements

M.Sc. or Ph.D. in Electrical or Computer Engineering (as stated in the posting).

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.