Analog Circuit Design Engineer

Job Title

Analog Circuit Design Engineer

Role Summary

Senior mixed-signal design engineer responsible for architecting, designing, and delivering analog and mixed-signal IP blocks for FPGAs, including regulators, bandgaps, ADCs, clocking circuits, and high-speed I/O. The role spans schematic design, pre-/post-layout optimization, reliability analysis, and post-silicon debug in advanced CMOS process nodes.

Experience Level

Senior level — expects experienced engineer (10+ years) with a track record of analog/mixed-signal and high-speed IO design.

Responsibilities

Deliver and own mixed-signal IP from architecture through silicon validation and productization. Collaborate across disciplines to integrate and qualify IP.

• Lead technical path-finding, architecture trade-offs, and micro-architecture for analog/mixed-signal blocks.
• Design and optimize circuit schematics; perform pre-layout and post-layout simulations and optimization across PVT and process variation.
• Define layout planning requirements (floorplan, routing, matching, metal grid) and work with layout teams.
• Generate design collateral: integration specs, timing and power models, IBIS/ICCT data, reliability and EOS analysis.
• Develop and own verification plans covering functionality, performance, and reliability for high-volume products.
• Perform post-silicon data analysis, debug, and implement design enhancements.
• Participate in and contribute to design reviews; represent the analog team in cross-functional meetings.
• Coordinate with external IP vendors as the analog design point of contact.

Requirements

Must-have technical skills and experience required to perform the role. Preferred items are noted separately.

• 10+ years of professional experience in analog/mixed-signal, high-speed, or high-voltage IO design.
• Direct hands-on design experience with amplifiers, comparators, regulators, ADCs, and high-speed transmit/receive circuits (SerDes, PAM-4, PCIe, DDR).
• Experience with analog/mixed-signal design and layout flow, including running post-layout simulations and extraction tools.
• Strong understanding of design trade-offs, process variation, aging, and reliability in modern CMOS technologies.
• Proficiency with circuit design and simulation tools (e.g., Virtuoso, SPICE, StarRC, Totem).
• Familiarity with Verilog, static timing analysis, UPF, and mixed-signal integration considerations.
• Good communication, prioritization, and cross-functional collaboration skills; able to mentor junior engineers.
• Nice-to-have: specific experience with high-speed receiver design.

Education Requirements

Required — BSEE, MSEE, or PhD in Electrical Engineering, or equivalent technical experience. The posting explicitly accepts equivalent practical experience in lieu of listed degrees.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.