AI-Driven ASIC Physical Design Principal Engineer
Cisco SystemsJob Title
AI-Driven ASIC Physical Design Principal Engineer
Role Summary
Join the Common Hardware Group to drive AI-assisted automation for ASIC physical design and timing sign-off. The role focuses on integrating large language models and tool feedback loops into placement, routing, and timing workflows to reduce design cycle time and improve Design QoR.
The engineer will collaborate with physical design teams, own the developer loop from prototype to production, and deliver measurable automation integrated with EDA tools.
Experience Level
Senior-level. The posting specifies advanced senior experience (examples given: Bachelor's +15 years, Master's +12 years, PhD +7 years).
Responsibilities
Primary responsibilities center on building AI-driven automation and production-grade integration with EDA tools.
- Collaborate with physical design teams to identify high-value automation targets (timing triage, congestion root-cause analysis, floorplan suggestions).
- Evaluate and benchmark LLM-generated outputs versus ground truth for Design QoR, timing impact, and sign-off compliance.
- Own the developer loop: prototype, evaluate, and productionize solutions focused on reducing design cycle time.
- Design agentic PnR workflows where an LLM iterates on placement, routing, and timing constraints using tool feedback.
- Create retrieval-augmented pipelines indexing PDKs, design rules, sign-off checklists, and runbooks for LLM reference.
- Author and maintain Tcl bridge scripts to convert LLM suggestions into executable EDA tool commands.
- Develop prompt architectures to interpret STA timing reports, DRC logs, congestion maps, and power analysis outputs.
Requirements
Must-have technical skills and experience for successful execution of the role. Preferred items are noted separately.
- Extensive ASIC physical design and sign-off experience at a senior level.
- Proficient in Python and experienced in leveraging AI tools via accurate prompting.
- Experience building an MCP-based wrapper layer connecting an LLM (Claude) to EDA tools (e.g., Innovus, ICC2, Calibre) for real-time interactions.
- Experience developing EDA copilots or AI-assisted design tools and working with Docker/containerized EDA environments.
- Experience with machine-learning-driven placement and routing (MLPD / ML-driven PnR).
- Familiarity with OpenAI APIs (e.g., GPT-4o) and vector databases such as Pinecone or Weaviate.
- Strong scripting ability (Tcl) to translate LLM outputs into tool commands and workflows.
- Excellent problem solving and the ability to measure and validate design QoR and timing impacts.
- Nice-to-have: experience with RTL-to-GDSII flow, design tapeouts at advanced nodes (7nm/5nm/3nm), and additional EDA tools (Tempus/PrimeTime, Redhawk/Voltus, Pegasus).
Education Requirements
Minimum qualifications specify degree + experience combinations: Bachelor's degree in Engineering with 15+ years ASIC experience; Master's degree in Engineering with 12+ years ASIC experience; or PhD in Engineering with 7+ years ASIC experience. Field: Engineering (e.g., electrical/computer/ASIC-related).
About the Company
Company: Cisco Systems
Headquarters: San Jose, CA, United States
Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).
