Agentic AI Engineer

Job Title

Agentic AI Engineer

Role Summary

Join Cadence's applied AI team to develop agentic systems for semiconductor design. Work with senior AI engineers and chip-design experts on model training, retrieval and knowledge engineering, and production agent tooling. Production-quality code you write will ship in customer-facing AI products.

Experience Level

Entry-level / Early-career. Role targets recent graduates and early-career engineers (graduating 2025–2026; recent grads welcome).

Responsibilities

Key responsibilities include:

• Train, fine-tune, distill, and evaluate LLMs/SLMs and embedding models for EDA-specific tasks using techniques such as LoRA/PEFT and instruction tuning.
• Build retrieval pipelines, prompt scaffolds, and tool-calling specifications to supply relevant design context (RTL, logs, reports, methodology docs) within token and latency constraints.
• Design and tune knowledge-graph schemas and optimize ingestion and queries for graph DBs and vector stores to keep retrieval accurate and fast.
• Implement and harden agent components: tools, memory, multi-hop reasoning patterns, and guardrails; triage and iterate on production failures.
• Curate, clean, and label datasets from EDA artifacts; develop synthetic-data and self-improvement loops where appropriate.
• Develop offline benchmarks and online telemetry to define success criteria and prevent regressions.
• Collaborate with senior engineers and domain experts; learn EDA workflows relevant to the product.

Requirements

Must-have qualifications:

• Strong fundamentals in deep learning, transformers, and LLM mechanics (attention, tokenization, context windows, decoding).
• Practical hands-on experience with at least two of: LLM fine-tuning, RAG/retrieval, agentic frameworks, knowledge graphs, vector databases (via coursework, internships, OSS, or projects).
• Proficient Python engineering; comfortable with PyTorch and Hugging Face; writes clean, tested, version-controlled code.
• Curiosity about silicon/chip design and willingness to learn the domain on the job.
• Strong written and verbal communication; bias toward shipping working code.

Nice-to-have:

• Prior AI/ML internship with shipped artifacts.
• Experience with agentic frameworks (e.g., LangGraph, AutoGen), graph DBs (Neo4j, ArangoDB) or vector DBs (Qdrant, Weaviate, pgvector, Chroma).
• ML systems or infra experience (vLLM, TGI, Triton, distributed training, GPU performance tuning, quantization).
• Background in compilers, formal methods, hardware description languages (Verilog/SystemVerilog/Chisel), EDA tools, publications, or OSS contributions.

Education Requirements

Bachelor's, Master's, or PhD in Computer Science, Electrical Engineering, ECE, AI/ML, or a closely related technical field. The role targets recent graduates (graduating 2025–2026); recent grads and early-career candidates are welcome.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.