Advanced Packaging Design Verification & Physical Validation Engineer

Job Title

Advanced Packaging Design Verification & Physical Validation Engineer

Role Summary

Join the Advanced Packaging Design team in Burlington, VT to own physical verification and validation for complex multi-die and advanced package architectures. You will run and improve DRC, LVS, and DFM flows, integrate validation earlier in the design cycle, and work with layout designers, package architects, and supply partners to ensure manufacturable, high-quality package designs.

This is a hands-on engineering role focused on process refinement, automation, and delivering reliable verification results that accelerate time-to-market.

Experience Level

Mid-level — requires approximately 3+ years of semiconductor design or manufacturing experience.

Responsibilities

Primary responsibilities focus on execution and improvement of physical verification flows and collaborating across design and manufacturing teams.

• Execute PKG floor-planning checks and full DRC, LVS, and DFM verification flows for advanced packaging designs.
• Integrate automated validation checkpoints early in the design cycle (shift-left) to reduce late-stage iterations.
• Identify verification pipeline bottlenecks and implement automation, scripts, or improved design kits to increase efficiency.
• Investigate and resolve complex violation reports in collaboration with package architects, layout designers, and foundry/supply partners.
• Document verification processes and train engineers on new methodologies and tool flows.

Requirements

Must-have technical skills and qualifications for immediate contribution.

• 3+ years of experience in semiconductor design or manufacturing roles (experience detail moved to Education Requirements).
• Proven track record driving quality improvement, design validation, or process validation.
• Strong scripting and automation skills (TCL, Python, Perl, or Skill) to develop and run verification flows and data analysis.
• Experience running and debugging physical verification on complex layouts (DRC, LVS, DFM).
• Familiarity with industry physical verification tools (examples: Siemens Calibre, Synopsys IC Validator, Cadence Pegasus).
• Strong analytical problem-solving, clear communication across R&D, layout, and external partners, and ability to work in a fast-paced R&D environment.
• Must be eligible to access export-controlled technology as required by applicable U.S. export regulations.

Nice-to-have:

• Experience with advanced packaging technologies (2.5D/3D IC, chiplets, CoWoS, interposers, high-density fan-out).
• Experience developing or refining design kits and foundry-specific verification methodologies.

Education Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field, plus 3+ years of experience in semiconductor design or manufacturing roles.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.