Advanced Package Technology, Principal Engineer

Job Title

Advanced Package Technology, Principal Engineer

Role Summary

Lead development of advanced package architectures and technologies for high-performance computing, AI accelerators, and networking products. Work across silicon, package, thermal, mechanical and supply-chain teams to define, validate and productize 2.5D/3D and co-packaged solutions.

Experience Level

Senior / Principal level. Typical experience: 8–10 years with Bachelor's/Master's or 5+ years with a PhD/post-doc (as specified in Education Requirements).

Responsibilities

Own technical strategy and delivery for advanced package solutions and collaborate with internal and external partners to bring technologies to volume readiness.

• Define package architectures (chiplet topology, interposer/substrate scaling, PDN strategy, thermal envelope) and lead co-design with silicon and system teams.
• Develop packaging technology roadmaps and evaluate novel concepts; perform feasibility, routing, SI/PI and thermal studies.
• Lead material selection, substrate stack-up definition, mechanical modeling, and reliability analysis.
• Work with OSATs, foundries and substrate vendors to assess process capability, manufacturability, yield and cost; drive qualification to volume readiness.
• Create proof-of-concept samples and transition successful concepts into productizable technologies and IP.
• Manage cross-functional programs and influence internal stakeholders and external partners to align roadmaps and delivery.

Requirements

Must-have technical skills, tools and experience.

• Proven experience in advanced package and substrate technologies, including material/process understanding, component- and board-level reliability, warpage and thermal management.
• Deep knowledge of signal integrity and power integrity: transmission line theory, electromigration, SI/PI simulation and analysis for 2.5D/3D packages and interfaces to memory, interposers, substrates and PCBs.
• Hands-on experience with SI/PI and EM tools such as Cadence Sigrity PowerSI, Ansys SIwave, Ansys HFSS, Cadence Clarity; ability to specify which simulations are required and correlate sims to measurements.
• Routing feasibility and layout experience using Cadence APD or PCB editors; understanding of chip-package interactions and failure mechanisms.
• Experience managing suppliers (substrate manufacturers, OSATs, foundries) and driving supplier programs to meet manufacturability and cost targets.
• Strong program management, communication, presentation and documentation skills; ability to work across time zones and influence senior stakeholders.

Nice-to-have:

• Experience with data center AI accelerators, networking silicon, HPC platforms, board/system/rack-level integration.
• Experience with VNA and TDR measurements for package/PCB characterization; experience setting technology roadmaps and driving cross-company supplier programs.
• Experience with silicon disaggregation/reaggregation and memory integration (chiplet ecosystems).

Education Requirements

Bachelor's or Master’s degree in mechanical engineering, materials science or a related field with ~8–10 years of relevant professional experience; or a PhD degree or post-doctoral experience with 5+ years of relevant experience. (Degree and field-of-study language extracted from the posting.)

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.