Advanced Package Technology, Principal Engineer

Job Title

Advanced Package Technology, Principal Engineer

Role Summary

Lead R&D and technology development for advanced semiconductor packaging targeted at high-performance computing, AI accelerators, and networking products. Drive package architecture, signal and power integrity, thermal and mechanical reliability, manufacturability, and vendor/OSAT collaboration to bring new multi-chip and 2.5D/3D packaging technologies to production.

Experience Level

Senior / Principal level. Typical experience guidance provided by the employer: senior-level technical leadership with substantial industry experience (see Education Requirements for specific years tied to degree level).

Responsibilities

Work across silicon, package, and manufacturing teams to define and deliver advanced package technologies.

• Develop packaging technology roadmaps for AI XPU, XPU-attach and switch products.
• Create and evaluate new package technology concepts; perform routing feasibility, signal and power integrity studies, and productize successful proofs of concept.
• Define package architecture: chiplet topology, interposer/substrate scaling, PDN strategy, and thermal/mechanical envelopes.
• Lead co-design with silicon floorplanning, PDN modeling, thermal/mechanical reliability and material/stack-up selection.
• Collaborate with OSATs, foundries and substrate manufacturers to assess process capability, manufacturability, yield and cost.
• Drive package qualification, reliability validation and readiness for volume manufacturing.
• Manage cross-functional programs and communicate technical decisions to internal stakeholders and external vendors.

Requirements

Must-have technical skills and experience required to perform the role.

• Proven experience with advanced package and substrate technologies, materials, and component/board-level reliability including warpage and thermal management.
• Deep expertise in signal and power integrity for 2.5D/3D packages, including interface with memory, interposers, substrates and PCBs; ability to perform PDN verification and signal routing optimization.
• Hands-on experience with EM and SI tools and workflows such as Cadence Sigrity PowerSI, Ansys SIwave, Ansys HFSS, Cadence Clarity (or equivalent) and ability to correlate simulation with measurements.
• Routing feasibility and layout experience using tools such as Cadence APD or PCB editor.
• Experience working with OSATs, substrate manufacturers and material vendors; ability to influence vendor roadmaps and drive supplier programs.
• Program management and cross-functional leadership skills; strong written and verbal communication and documentation ability.

Education Requirements

Bachelor's or master's degree in Mechanical Engineering, Material Science or a related technical field (typical experience: Bachelor's + 8–10 years), or PhD / post-doc in a related field with ~5+ years of relevant experience. Equivalent industry experience in advanced packaging and related domains may be considered where specified by the employer.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.