3D Memory Chip Architect and Design, Principal Engineer

Job Title

3D Memory Chip Architect and Design, Principal Engineer

Role Summary

Principal engineer on the Qualcomm Custom Memory Team (Process & Package Solutions Group) focused on 3D memory and near-memory compute architectures for data center, mobile, compute, and XR systems.

The role assesses and optimizes 3D DRAM/FLASH and near-memory compute organization to meet system KPIs (bandwidth, latency, power, thermal, area) and works across packaging, SoC, memory controller, performance modeling, and emulation teams.

Experience Level

Senior — typical experience expectations: 8+ years with a Bachelor's, 7+ years with a Master's, or 6+ years with a PhD in a technical field (see Education Requirements for details).

Responsibilities

Work across architecture, modeling, and physical design to deliver high-bandwidth, high-efficiency 3D memory systems and their integration with compute fabrics.

• Develop and optimize 3D DRAM/FLASH organization and near-memory compute architectures to maximize density, TOPS/mm2, and TOPS/W.
• Develop and validate models for 3D memory performance, power, and yield as functions of bank layout, TSVs, and power distribution.
• Design high-bandwidth fabrics to distribute data from 3D memory arrays to near-memory compute units for AI, compute, mobile, and XR workloads.
• Define robust power-distribution topologies for 3D stacks and evaluate thermal/power constraints.
• Simulate and emulate system-level performance across representative workloads.
• Floorplan 3D memory chips and design memory-array control structures considering 3D integration, testability, and repairability.
• Specify and evaluate interconnects and IO standards (UCIe, UAL, LPDDR, HBM3/4, PCIe) for 3D-integrated systems.

Requirements

Key technical skills and domain experience required or strongly preferred. Must-have items are listed first; nice-to-have items follow.

• Must-have: Significant experience in ASIC design, verification, validation, or integration with demonstrable system-level understanding.
• Must-have: Strong knowledge of memory architecture (bank organization, signaling), buses, IO, and 2.5D/3D integration constraints.
• Must-have: Experience developing and validating performance and power models for memory or SoC components.
• Nice-to-have: RTL, circuit, and system design experience to model and optimize dataflow; Verilog/Verilog-A/Verilog-AMS modeling experience is a plus.
• Nice-to-have: Experience with DRAM/FLASH architecture and familiarity with datasheets and IO interfaces.
• Nice-to-have: Background in memory circuit design (SRAM/DRAM/FLASH/ROM/OPT) and mixed-signal ASIC design.
• Nice-to-have: Proficiency with EDA tools, Matlab, and Python; familiarity with performance modeling and emulation flows.
• Soft skills: Self-starter, clear communicator, strong analytical and problem-solving skills, and ability to work independently and in cross-functional teams.

Education Requirements

Bachelor's, Master's, or PhD in Science, Engineering, or a related technical field are specified. Typical experience mapping in the posting: Bachelor's +8 years, Master's +7 years, or PhD +6 years. Preferred fields mentioned include Electrical Engineering and Computer Science.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.