3D Memory Chip Architect and Design, Principal Engineer

Job Title

3D Memory Chip Architect and Design, Principal Engineer

Role Summary

Lead the architecture and design of 3D memory systems and near-memory compute fabrics to optimize bandwidth, latency, power, thermal and area for mobile, compute, XR and data-center applications. Work cross-functionally with process & packaging, SoC, AI/compute architects, memory controller, performance modeling and emulation teams to deliver architected solutions under 3D integration constraints.

Experience Level

Senior / Principal level. Expect a senior engineer with substantial ASIC and memory-architecture experience (see Education Requirements for degree-year equivalencies).

Responsibilities

Design, evaluate, and optimize 3D memory architectures and their integration with compute fabrics; provide modeling and implementation guidance across teams.

• Develop and optimize 3D DRAM/FLASH organizations and near-memory compute architectures for density, TOPS/mm2 and TOPS/W.
• Build and validate performance, power and yield models across bank, TSV and power-distribution choices.
• Architect high-bandwidth fabrics to distribute data from 3D memory arrays to near-memory compute units across workloads.
• Design robust power-distribution topologies for 3D stacks and analyze thermal and power constraints.
• Simulate and emulate system performance for AI, compute and mobile workloads to inform architecture trade-offs.
• Floorplan 3D memory chips and design array control structures considering 3D manufacturing, testability and repairability.
• Collaborate with packaging, SoC, memory-controller and performance teams and provide timely architecture/design feedback.

Requirements

Must-have technical skills, relevant experience, and professional attributes. Degree requirements and degree/experience equivalencies are summarized under Education Requirements below.

• Must-have: Substantial ASIC design, verification, validation or integration experience (senior-level; typically multi-year experience — see Education Requirements for specifics).
• Must-have: Deep understanding of memory bank organization, signaling, bus/IO and compute fabrics, and of 2.5D/3D integration and advanced packaging constraints.
• Must-have: Experience building and validating performance/power/yield models for memory systems and analyzing trade-offs.
• Must-have: Familiarity with high-speed connection fabrics and interfaces such as UCIe, UAL, LPDDR, HBM3/4 and PCIe.
• Must-have: Ability to simulate/emulate system-level performance and floorplan memory arrays under manufacturing and repairability constraints.
• Nice-to-have: RTL, circuit and system design experience; Verilog/Verilog-A/Verilog-AMS modeling skills.
• Nice-to-have: Experience in DRAM/FLASH architecture assessment and memory circuit design (SRAM/DRAM/FLASH/ROM/OPT).
• Nice-to-have: Proficiency with EDA tools, MATLAB and Python; scripting (Perl/Python) and C/C++ programming experience.
• Soft skills: Self-starter, strong communication, teamwork, problem-solving and analytical abilities.

Education Requirements

Minimum qualifications specify degree-plus-experience equivalencies: Bachelor's degree in Science, Engineering or related field with 8+ years of relevant ASIC design/verification/validation/integration experience; OR Master's with 7+ years; OR PhD with 6+ years. Preferred: Master's or PhD in Electrical Engineering, Computer Science or a related field. Equivalent practical experience that meets the experience requirements is acceptable as described above.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.