"Synopsys ICC2 Floorplan Engineer Jobs: Find Back-End PD Roles"

Floorplanning is where a chip's physical shape gets decided, and on Synopsys flows that decision happens in IC Compiler 2. A floorplan engineer sets the die and core area, places the hard macros, assigns I/O, and builds the power rings and stripes before detailed placement ever runs. Get it wrong and every downstream stage inherits congestion and timing problems that are expensive to unwind.

The day-to-day is command-driven. You run create_floorplan, place_pins, and create_power_straps, and you develop a feel for macro placement that keeps routing channels open on congested blocks. Early timing budgets come from pre-placement analysis, so you are estimating what the block can close before the tool has done any real work. This is the broader floorplan engineer discipline, run inside the Synopsys back-end flow specifically.

Demand concentrates at companies running multi-block or full-chip implementation on advanced nodes: 5nm and 3nm mobile SoCs, data center CPUs, and AI accelerators where macro density and power delivery are the hard constraints. These are Synopsys-primary shops that pair ICC2 with Fusion Compiler for physical synthesis feedback.

That feedback loop is what separates a strong floorplan engineer from someone who places macros by eye. Running physical synthesis against a floorplan gives you timing and congestion numbers for that exact configuration, so you can weigh aspect ratios, channel widths, and macro positions against real quality metrics. Roles that lean fully into the tool show up as Synopsys ICC2 engineer positions.

Floorplan engineers also sit at the chip-to-package boundary. You align I/O pin placement with package ball grid constraints, escape routing, and power bump placement, usually in direct conversation with a package engineer. ICC2's package assembly view lets both sides see chip I/O and substrate routing together, which is where most of the interface trade-offs actually get resolved.

The interview line that lands is a real tapeout where you owned the floorplan: the macro strategy you chose, the congestion you headed off, the timing budget you closed. Save a search on semidesignjobs.com and you will get an email when a back-end PD role matching your filters opens.

FAQ

What ICC2 commands are most important for floorplan engineer jobs?

The core set is initialize_floorplan for die and core area setup, place_pins for I/O assignment, create_placement_blockage for macro exclusion regions, and create_power_straps for power grid planning. Comfort with save_block and restore_block matters too, since floorplanning is iterative and you will be managing several configurations at once as you tune placement and power.

How does physical synthesis feedback improve ICC2 floorplanning?

Running physical synthesis in Fusion Compiler or DC-Topo mode produces timing and congestion estimates tied to a specific floorplan. That lets you evaluate trade-offs, such as adjusting macro placement, block aspect ratios, or channel widths, against quantitative quality metrics instead of geometric intuition. It turns floorplanning from a guessing exercise into a measured one.

How does ICC2 floorplanning interact with package substrate design?

Floorplan engineers align chip I/O pin placement with package ball grid constraints, escape routing requirements, and power delivery bump placement, working directly with package engineers. ICC2's package assembly view shows chip I/O placement and package substrate routing together, so both teams can optimize the chip-to-package interface in one shared view rather than trading files back and forth.