Low-Power ASIC Design: UPF, Power Domains, and IEEE 1801 Flows

Power has overtaken area as the dominant constraint in modern ASIC design. At 5nm and below, leakage alone can consume 30-40% of the total power budget before a single gate switches. Mobile SoCs, AI inference chips, and automotive-grade ASICs all have hard power envelopes that can't be met with RTL tricks alone. Getting there requires a structured, tool-aware flow built around the Unified Power Format standard: IEEE 1801-2024 (UPF 4.0).

UPF isn't just a file format. It's the mechanism by which a chip's power intent, which domains can shut off, which signals need isolation, which registers need to retain state, is propagated consistently from RTL through synthesis, place-and-route, signoff, and verification. Getting UPF right early prevents costly ECOs late in the flow. Getting it wrong creates silicon failures that don't show up until post-silicon bring-up.

This article covers the core concepts every ASIC engineer working on low-power designs needs to understand: the power dissipation model, UPF constructs, the special cells that implement power intent, the RTL-to-GDSII flow, and power-aware verification. If you're a physical design engineer or ASIC design engineer who hasn't yet worked deeply with multi-voltage designs, this is where to start.

Key Takeaways - UPF (IEEE 1801) is the industry-standard language for specifying power intent across the full ASIC design and verification flow. - Three categories of special cells - isolation cells, level shifters, and retention registers - are the physical implementation of UPF power domain boundaries. - Power-aware verification must run in parallel with RTL development; catching isolation or retention errors in simulation is orders of magnitude cheaper than catching them in silicon.

Why Power is a First-Class Constraint Now

CMOS power dissipation comes in two forms. Dynamic power scales with activity: P_dynamic = alpha * C * V^2 * f, where alpha is the switching activity factor. Reducing voltage is the highest-leverage lever, since power drops with the square of supply voltage. Static (leakage) power, driven primarily by subthreshold and gate-oxide leakage, grows exponentially as process nodes shrink and threshold voltages are pushed lower to maintain performance.

At 28nm and above, leakage was manageable with careful threshold voltage selection. At 7nm and below, the leakage problem is qualitatively different. A large SoC sitting idle can burn hundreds of milliwatts just from leakage in blocks that aren't being used. This is what drives power gating: if you can completely cut the supply to an idle block, you zero out its leakage contribution entirely.

The practical consequence for design teams is that power management can't be bolted on at the end of a project. The power architecture, which domains exist, what their nominal and retention voltage levels are, and how they sequence during power-up and power-down, has to be defined at the architecture phase. That definition lives in a UPF file, and it governs what every downstream tool does.

The UPF Standard: What IEEE 1801 Defines

UPF (Unified Power Format), standardized as IEEE 1801, is a Tcl-based specification language that captures a design's power intent in a form that EDA tools can read and enforce. The current revision is IEEE 1801-2024 (UPF 4.0), released in late 2024 after IEEE made it available through the Accellera GET Program.

UPF 4.0 introduced several meaningful additions over UPF 3.0. Value Conversion Methods (VCMs) and supply tunneling bridge analog and mixed-signal components into the power intent model. Refinable macros let IP providers ship "soft IP" with parameterizable power intent, so integrators can adapt it to their supply topology. Virtual supply nets allow modeling of supplies that don't exist in the RTL hierarchy but need to be represented in the power network.

For the vast majority of digital ASIC designs, UPF 2.1 and 3.0 constructs remain the working vocabulary. A UPF file typically defines:

• Power domains: Logical groupings of design elements that share a power state. Each domain has a primary supply.
• Supply nets and supply sets: The named voltage rails that supply each domain. A supply set bundles multiple rails (power, ground, nwell) into a logical group.
• Power states: Named combinations of on/off and voltage levels for the design's supply sets.
• Power state tables (PSTs): The legal combinations of domain states across the full chip, and the transitions between them.
• Level shifter and isolation cell strategies: Rules that tell synthesis and P&R where to insert special cells at domain crossings.
• Retention strategies: Which registers must retain their state during power-down, and the save/restore sequencing.

A minimal two-domain UPF for a design with an always-on domain and a power-gated block looks roughly like this:

create_power_domain PD_TOP -include_scope
create_power_domain PD_AUDIO -elements {u_audio_dsp}

create_supply_net VDD   -domain PD_TOP
create_supply_net VSS   -domain PD_TOP
create_supply_net VDD_A -domain PD_AUDIO

set_domain_supply_net PD_TOP   -primary_power_net VDD   -primary_ground_net VSS
set_domain_supply_net PD_AUDIO -primary_power_net VDD_A -primary_ground_net VSS

add_power_state PD_AUDIO.primary -state {ON  {supply_expr {VDD_A == {FULL_ON, 0.8}}}}
add_power_state PD_AUDIO.primary -state {OFF {supply_expr {VDD_A == {OFF}}}}

set_isolation ISO_AUDIO -domain PD_AUDIO -applies_to outputs \
    -clamp_value 0 -isolation_power_net VDD -isolation_ground_net VSS
use_interface_cell ISO_CELL_D1 -strategy ISO_AUDIO -lib_cells {ISO_AND2_X1}

set_retention RET_AUDIO -domain PD_AUDIO -retention_power_net VDD \
    -retention_ground_net VSS
use_interface_cell RET_CELL -strategy RET_AUDIO -lib_cells {DFFR_X1}

ChipVerify's UPF reference is a practical starting point for understanding the full command set and common patterns.

Special Cells: The Physical Implementation of Power Intent

Power domain boundaries require special cells that standard synthesis won't infer on its own. UPF-aware tools insert these automatically based on the strategies defined in the UPF file, but engineers need to understand what each cell does and why it's needed.

Isolation Cells

When a power-gated block drives signals into an always-on domain, the driven logic sees floating or undefined inputs when the source domain is off. Isolation cells clamp those outputs to a safe known value (typically logic 0 for active-high signals, logic 1 for active-low). They sit at the output boundary of the power-gated domain and are powered by the always-on supply.

The clamp value matters for functional correctness. A wrong clamp value can cause the receiving logic to take an incorrect path during power transitions, which may not be caught by standard functional simulation if the test doesn't exercise power sequencing.

Level Shifters

When signals cross between domains operating at different supply voltages, a level shifter is required. A standard-cell driving into a higher-voltage domain will produce output swings that don't reach the switching threshold of the receiver. Level shifters come in high-to-low and low-to-high variants. For bidirectional interfaces, dual-supply level shifters handle both directions. In UPF, level shifter insertion is controlled by set_level_shifter strategies.

Retention Registers

Power gating erases register state. For blocks where state must survive power-down, retention registers add a secondary "shadow" latch powered by the always-on supply. On a save event (before power-down), state is copied from the main flip-flop to the shadow. On restore (after power-up), state is written back. Retention flops are 25-30% larger than standard flops in area, so retention strategy should be applied selectively to only the registers where state preservation is actually required.

Power Switches (Header and Footer Cells)

Power gating is implemented with header cells (PMOS switches on the supply rail) or footer cells (NMOS switches on the ground rail). These are arrayed across the power-gated domain in P&R. Sizing the switch array requires careful analysis: too few switches and the IR drop during wake-up causes functional failures; too many and area and routing overhead grow unnecessarily.

The Low-Power ASIC Flow: RTL to GDSII

Low-power design flows with UPF differ from standard flows in several key stages:

Architecture and UPF authoring. Power domain partitioning happens at the SoC architecture phase. The chip architect defines which blocks can power-gate, which operate at reduced voltage (multi-VDD), and what the power state table looks like. This feeds directly into the UPF file. A poorly partitioned power domain structure is very difficult to fix after RTL is locked.

RTL coding with power awareness. RTL engineers need to avoid constructs that break power intent: unintended combinational paths from power-gated domains, missing enable qualifications that could corrupt always-on state during transitions, and clock enable structures that don't align with clock-gating cell insertion points.

Power-aware synthesis. Synopsys Design Compiler (DC) and Cadence Genus both read UPF during synthesis. They insert isolation cells and level shifters at domain crossings based on UPF strategies, and map retention registers from the target library. The netlist that comes out of synthesis is power-domain-aware, with all required special cells present.

Physical implementation. In Cadence Innovus or Synopsys Fusion Compiler, power planning includes per-domain power mesh definition, power switch array placement, and always-on ring routing. The UPF is re-read to guide these steps. IR drop analysis (static and dynamic) validates that the power network can support both steady-state and wake-up surge currents. For the details of what this looks like day-to-day, see the overview of physical design engineer roles.

Signoff. Power-aware STA must model all supply combinations defined in the power state table, not just the nominal operating state. Corners where a domain is at retention voltage while neighbors are at full voltage can expose setup violations that don't appear in standard timing runs.

Power-Aware Verification

Functional simulation with UPF requires a power-aware simulator. Cadence Xcelium and Synopsys VCS both support UPF-annotated simulation. The simulator models supply states, inserting corruption X-propagation when a domain is off and logic in that domain is accessed, which catches missing isolation or incorrect clamp values.

Cadence's low-power verification methodology formalizes the key checks: isolation completeness, level shifter correctness, retention save/restore sequencing, and power state transition coverage. Formal low-power verification tools, including Cadence JasperGold Power Apps and Synopsys VC LP, can exhaustively check UPF intent against the netlist without needing simulation vectors, which is especially valuable for finding isolation holes in complex hierarchical designs.

For verification engineers, low-power work adds several new responsibilities: writing power-aware UVM test sequences that exercise power state transitions, building power-domain coverage models, and coordinating with the physical design team on power switch controller interfaces. Low-power verification depth has become a concrete differentiator in senior verification engineer hiring.

Clock Gating: The Easiest Win

Before reaching for power gating, most designs exhaust clock gating opportunities first. Clock gating inserts an enable-qualified latch into the clock path of a register bank, preventing unnecessary switching when the bank's output isn't needed. A properly clock-gated design can cut dynamic power 20-40% in activity-sparse blocks. Synthesis tools infer clock gating automatically from RTL enable conditions when the coding style is clean, but the effectiveness depends heavily on how well the RTL is structured.

The key RTL pattern that enables clock gating inference is a qualified enable on all flip-flop inputs in a bank:

always_ff @(posedge clk) begin
    if (enable)
        data_reg <= data_in;
end

Synthesis maps this to an ICG (integrated clock gate) cell, which isolates the clock from the flip-flop when enable is low. Checking the synthesized netlist's clock gating coverage, typically reported as a percentage of register bits covered by an ICG, is a standard post-synthesis quality check.

Career Implications

Low-power design expertise is in genuine short supply relative to demand. Every AI accelerator, mobile AP, and IoT SoC being designed today has a non-trivial power architecture. Engineers who understand UPF, power domain partitioning, and power-aware verification are valuable across the full design stack: RTL, synthesis, physical implementation, and verification all have low-power-specific skill requirements.

At the senior level, setting up a clean power domain architecture early, before RTL is locked, is one of the highest-leverage things a design team can do. Getting it wrong propagates pain through every downstream phase. Getting it right is largely invisible, which is the hallmark of good architecture work.

If you're building out this skill set, the best practical path is working through actual UPF files on real designs, running power-aware simulation, and reading the tool-specific application notes from Synopsys and Cadence on their low-power flows. The standard itself (IEEE 1801-2024) is now available free through the Accellera GET Program.

Conclusion

Low-power ASIC design has moved from an optimization exercise to a fundamental constraint that shapes architecture, RTL, implementation, and verification in parallel. UPF (IEEE 1801) is the standard that holds this all together, and understanding it is increasingly a baseline expectation for mid-to-senior ASIC engineers rather than a specialty.

The skill set is concrete: know how to author and read UPF, understand what isolation cells, level shifters, retention registers, and power switches do and why they're needed, and know how to run and interpret power-aware simulation. From there, the tool-specific details for Synopsys or Cadence flows are learnable on the job.

Browse open roles requiring low-power design skills on Semiconductor Design Jobs, including ASIC design positions across fabless companies and vertically integrated semiconductor teams working at advanced nodes.