ASIC Design Engineer Jobs: Find Your Next Role in Chip Design
ASIC design hiring splits across two distinct domains right now: steady volume work for mobile SoC, automotive, and networking silicon, and a smaller but faster wave of AI accelerator and hyperscaler in-house projects. Both are hiring. If you're scanning postings on semidesignjobs.com, you'll see roles tagged for mobile SoC, data center, AI accelerator, automotive, and networking, in roughly that order of volume.
Most listings ask for SystemVerilog or Verilog at the block level, working knowledge of synthesis (Design Compiler or Genus), and the muscle memory to hand off lint-clean and CDC-clean RTL to verification and physical design. Microarchitecture judgment matters more than tool experience as you get senior. At the staff level, interviews push on memory hierarchy, interconnect, and power-aware design choices, not Verilog syntax.
The employer roster is familiar: Apple, Nvidia, Qualcomm, AMD, Intel, Marvell, plus a long tail of well-funded AI chip startups. Hyperscaler in-house silicon teams at Google, AWS, and Microsoft are now a significant source of openings and tend to pay at or above the tier-one fabless companies. Browse the current company list to filter by employer and stage.
Compensation is bifurcated. Entry-level US roles land at $110K to $140K base. By staff, total comp at Apple, Nvidia, AMD, and the hyperscalers routinely clears $300K once equity vests. Senior engineers at AI startups can hit similar numbers when the company performs, with more upside and more risk in the equity. For a level-by-level breakdown, the salary guide tracks current numbers by region and seniority band.
The market isn't uniformly hot. Consumer-facing silicon hiring slowed in 2024 and stayed choppy through early 2025; AI accelerator, automotive, and networking remain the strongest hiring areas. RTL-focused openings overlap heavily with general ASIC postings, and physical design roles are usually a separate listing at the same employers.
Save a search on semidesignjobs.com for the role types, locations, and company stages you care about. New postings hit your inbox automatically, which is the lowest-effort way to keep an eye on the market if you're passive.
FAQ
What qualifications do ASIC design engineer jobs ask for?
Most postings ask for a BS or MS in EE or CE plus production RTL experience in SystemVerilog or Verilog. Hiring managers weight specific tapeout experience and familiarity with the full front-end flow from RTL through synthesis and timing signoff. A clean GitHub of synthesizable RTL helps for early-career applicants without tapeouts on the resume.
Where are most ASIC design engineer jobs located?
Silicon Valley remains the largest market by a wide margin, followed by San Diego, Austin, Seattle, and Boston. Hybrid is now the default at most companies. Fully remote postings are growing at startups and a handful of mid-size firms, but they remain a minority of the listings on any given week.
What salary should I expect from ASIC design engineer jobs?
Entry-level US engineers earn $110K to $140K base. Senior engineers at tier-one fabless companies routinely earn $200K to $300K+ in total comp including equity. Staff and principal levels at hyperscalers and Apple often exceed those numbers, particularly when equity refresh grants stack with strong stock performance.