DFT Engineer Positions: Find Design-for-Test Roles in IC

Every chip that goes to high-volume manufacturing needs DFT infrastructure, or the fab cannot separate passing dies from defective ones economically. That dependency makes DFT engineers essential, and the field stays undersupplied because the discipline sits at the intersection of RTL design, physical implementation, and manufacturing test methodology. Engineers who understand all three are rare.

Full-chip DFT architecture planning starts before RTL freeze: choosing scan compression ratios (often 64x or 128x with tools like Synopsys TestMAX or Siemens Tessent EDT), mapping out memory BIST strategy for embedded SRAMs and ROMs, and defining the IEEE 1149.1 JTAG or 1687 IJTAG access network. At-speed test requirements push engineers into transition fault and path-delay ATPG, which adds another layer of coordination with the timing signoff team. Pattern count and ATE time are real cost constraints: a test that runs 30 seconds per die kills unit economics at anything over low volume.

After synthesis, scan insertion runs through Synopsys TestMAX (the successor to DFT Compiler and TetraMAX) or Siemens Tessent, with final ATPG pattern generation deferred until after physical implementation produces a timing-clean netlist. SoC-level DFT adds hierarchical complexity: each IP block carries its own IEEE 1500 wrapper, and the top-level DFT team stitches access paths together without creating timing or routing violations. Browse DFT jobs on semidesignjobs.com filtered by seniority to find architecture-level and block-level openings separately.

IDMs and large fabless companies are the steadiest hirers. Intel, Samsung, and GlobalFoundries hire DFT engineers internally for process qualification and product test. On the fabless side, Qualcomm, AMD, Apple, Marvell, and Broadcom each run large DFT teams for their respective SoC families. AI chip startups building first-generation custom accelerators often need one senior DFT engineer who can own the full flow end-to-end. Automotive and high-reliability markets add ISO 26262 functional safety requirements on top of standard DFT, creating a specialized niche that commands a premium. ASIC design engineer positions and verification engineer openings are frequently browsed alongside DFT roles.

Mid-level DFT engineers in the US earn $140K-$190K base. Staff and principal engineers with full-chip SoC DFT ownership at large fabless companies reach $250K and above in total compensation. The salary guide breaks down ranges by seniority level and geography.

DFT is a good long-term bet for IC career stability. Demand is durable because test is non-negotiable in volume production, the practitioner base is smaller than RTL or verification, and the combination of ATPG skills with SoC-level architecture experience is genuinely hard to find. Save a search on semidesignjobs.com filtered for DFT or design-for-test tags, and new openings will reach your inbox when they go live.

FAQ

What tools are most commonly used in DFT engineer positions?

Synopsys TestMAX, the successor to DFT Compiler and TetraMAX, and Siemens Tessent are the dominant tools for scan insertion and ATPG. IEEE 1687 (IJTAG) and IEEE 1500 compliance is increasingly required for hierarchical DFT in complex SoCs. Some companies use Cadence tools for specific flows, but TestMAX and Tessent are the industry standard pair. Hands-on experience with at least one is expected; proficiency in both is a differentiator at senior levels.

How does DFT engineering fit into the overall ASIC design flow?

DFT architects engage before RTL freeze to plan scan architecture and BIST strategy. Scan insertion runs after synthesis; ATPG pattern generation follows physical implementation once a timing-clean netlist is available. DFT touches every major milestone in the ASIC flow and requires coordination with RTL, synthesis, physical design, and the ATE team at the foundry or OSAT. Late DFT engagement is a common source of schedule risk on tapeout projects.

Is DFT engineering a good career path for IC design professionals?

Yes. DFT is a specialized discipline with durable demand and relatively few deeply experienced practitioners at the senior and staff levels. Engineers who combine DFT expertise with an understanding of physical design constraints and manufacturing test economics are well-positioned for staff and principal-level roles. The field also has a clear technical ladder that stays individual-contributor for most of its range, which suits engineers who prefer depth over managing headcount.