Cadence Conformal LEC Engineer Jobs: Browse Equivalence Roles

Nobody tapes out on a netlist that has not passed equivalence checking. That single gate is why Cadence Conformal work stays funded through hiring freezes: if the compare fails at 2am the week of tapeout, someone has to know why.

Conformal is the Cadence logical equivalence checker and the main alternative to Synopsys Formality. It is native to the Cadence flow, so it is the default LEC at shops running synthesis into Innovus place and route.

Day to day you build Conformal compare sessions, teach the tool about transformations it would otherwise flag as failures, and pull apart non-equivalent points until you can say whether the netlist is wrong or the setup is.

Transformation guidance is the part that takes real experience. Scan chain insertion, clock gating, constant propagation, and retiming all restructure the netlist legitimately, and each one needs setup points and mapping so Conformal reads the change as intended. Get it wrong and you burn a day chasing a failure that was never a bug.

There is flow work too. Conformal gets wired into automated sign-off scripts so every netlist handoff runs LEC without anyone remembering to launch it. Hierarchical setups let block teams verify independently while top level treats the verified blocks as black boxes.

On a big SoC that hierarchy is not optional. Full-chip flat compare on a modern design will exhaust memory or run past any schedule you have, so the partitioning decisions you make early determine whether LEC is a background job or a two-week fire in the last month before tapeout.

Most of the demand sits at Cadence-primary shops: networking and storage controller teams at Marvell and Broadcom, mobile SoC groups, automotive silicon programs. Titles vary, so watch netlist engineer postings and ASIC synthesis roles as well. Both lean on Conformal for sign-off and often hire the same person.

Comp sits with implementation and sign-off engineers generally, roughly $130K to $180K base in the US at mid-level and higher at staff on advanced-node programs. Ranges by level and region are in our salary guide.

If you are targeting these roles, say which tapeouts you signed off and what you debugged. A hiring manager can tell the difference between someone who ran the script and someone who fixed the compare.

Save a search on semidesignjobs.com to get an email when a Conformal or LEC sign-off role opens.

FAQ

What design transformations require special handling in Cadence Conformal LEC?

Scan chain insertion, clock gating, constant propagation, synthesis restructuring, and retiming all change netlist structure in ways Conformal will otherwise report as equivalence failures. Engineers supply transformation guidance, meaning setup points and mapping commands, so the tool treats each structural change as intended behavior.

How does Cadence Conformal handle hierarchical LEC for large chip designs?

Conformal compares design blocks independently, which cuts the compute needed for a full-chip run. Each block team runs LEC on its own block, and top-level LEC then covers the integration netlist with the already-verified blocks treated as black boxes. That approach scales to the largest SoCs.

Can Cadence Conformal be used for FPGA-to-ASIC equivalence checking?

Yes. Conformal can compare an FPGA implementation mapped to FPGA primitives against an ASIC netlist or the source RTL to confirm functional equivalence during a port. Programs that prove out functionality on FPGA first and then migrate to an optimized ASIC use this regularly.