Cadence Design Systems Engineer Jobs: Open Roles
Cadence and Synopsys are the two names that turn up in almost every chip design flow, and a Cadence engineer sits on the tool side of that equation: building the EDA software and IP the rest of the industry uses to design silicon.
The roles split into a few tracks. EDA tool development means C++ for the core engines, Python or Tcl for scripting, and real fluency with the algorithms underneath placement, routing, timing, and simulation. IP roles lean on RTL or analog circuit skill, since you are shipping SerDes, DDR PHY, and PCIe blocks that customers drop straight into their own designs. Verification platform work sits closer to systems and hardware engineering, because Palladium emulation and Protium prototyping are physical boxes with their own software stacks.
The portfolio you might land on is large. On the EDA side there is Virtuoso for analog and mixed-signal, Innovus for place-and-route, Xcelium for simulation, and Jasper for formal verification. System analysis adds Clarity, Celsius, and Sigrity. The AI push, Cerebrus for RTL optimization and Optimality for system analysis, has opened ML engineering roles inside the EDA group that did not exist a few years ago. Cadence spends north of $1.2B a year on R&D, so the tool teams keep growing.
SemiDesignJobs pulls Cadence Design Systems engineer jobs from the major offices: San Jose and the wider Bay Area, Austin, Pittsburgh, Burlington in Massachusetts, and Noida and Pune in India. If you are weighing vendors, compare openings at Synopsys EDA engineer jobs, and check EDA engineer jobs in San Jose if you want to stay local. For the full field, browse our EDA jobs category.
Because you are competing for the same engineers as the big software companies, the pay reflects it. In the US, early-career EDA R&D engineers at Cadence generally start around $120K to $160K base, senior engineers move into the $180K to $230K range, and staff or principal engineers reach $250K to $350K in total comp once equity and bonus are counted. Application engineering roles that work directly with customers usually pay less on base and more on variable. Our semiconductor salary guide covers the wider picture.
Cadence keeps hiring as it pushes further into IP and AI-driven design. Create a profile on semidesignjobs.com, save a search, and you will hear about new Cadence openings as they post.
FAQ
What does a Cadence Design Systems engineer work on
Cadence engineers develop and maintain EDA tools like Innovus for place-and-route, Virtuoso for analog and mixed-signal, Spectre for simulation, and Xcelium for simulation and coverage. Others work on the digital and analog IP cores, SerDes, DDR PHY, and PCIe, that chip teams across the industry license and integrate.
What skills are most valued for Cadence Design Systems engineer jobs
Strong C++ and Python, deep knowledge of EDA algorithms, and hands-on IC design experience carry the most weight on the tool side. For IP roles, the bar is real RTL or analog circuit design expertise, since you are shipping blocks that customers rely on in production.
Are there Cadence Design Systems engineer jobs outside California
Yes. Cadence runs significant engineering teams in Austin, Burlington, and Pittsburgh, plus international offices including Noida and Pune in India. SemiDesignJobs lists every location attached to each Cadence posting so you can filter to where you want to work.