Zebu Flow Engineer

Job Title

Zebu Flow Engineer

Role Summary

Join SiFive's System Validation team to develop and maintain build and debug flows for modeling RISC‑V CPUs on hardware emulators (primarily Synopsys ZeBu) and FPGA platforms. The role focuses on automation of build/runtime flows, failure analysis, and collaboration with software and validation teams to validate processor designs.

Experience Level

Entry-level / early-career. The posting requests at least 1 year of relevant experience.

Responsibilities

Primary responsibilities include maintaining emulator/FPGA build flows and supporting hardware/software debug and validation.

• Design, build and maintain a modular flow for creating Synopsys ZeBu models using the internal SiFive build system.
• Port compilation steps into the SiFive wake-based build environment for integration with other flows.
• Perform root-cause and failure analysis across RISC‑V CPU hardware and software stacks.
• Use emulator debug features (waveform dumping) and hardware debuggers (ILA, JTAG) to troubleshoot designs.
• Formulate and test failure hypotheses through systematic elimination of causes.
• Develop and maintain Python-based automation and scripts to improve debug and runtime workflows.
• Integrate ZeBu runtime automation into the SiFive manager ecosystem and support cross-functional teams.

Requirements

Must-have technical skills and attributes; concise list of practical requirements and desirable skills.

• Strong understanding of digital/logic design concepts.
• Experience coding in Verilog and porting designs onto FPGA platforms.
• Practical experience with Linux and scripting in Python and Bash.
• Familiarity with hardware emulators or FPGA-based validation platforms (experience with Synopsys ZeBu is preferred).
• Ability to perform systematic debug and failure analysis; strong problem-solving discipline.
• Collaborative communicator comfortable working with software and validation engineering teams.
• Positive, proactive attitude and commitment to continuous learning.
• Nice-to-have: experience with wake-based build systems, ILA/JTAG debug workflows, or RISC‑V software ecosystem.

Education Requirements

Bachelor's or Master's degree in Computer Science or Electronics and Communication Engineering is required, with a minimum of 1 year of relevant experience.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.