Yield Development Engineer

Job Title

Yield Development Engineer

Role Summary

The Yield Development Engineer will identify and remove yield limiters across process, design and test to improve product quality and factory efficiency. The role is hands-on, requiring fault isolation, statistical analysis, and collaboration with design, test and process teams to implement process changes and support product introductions.

Experience Level

Mid-level. The posting specifies 3+ years of experience in semiconductor failure analysis or test engineering.

Responsibilities

Responsible for diagnosing yield issues and executing data-driven process improvements.

• Identify and analyze yield limiters using statistical techniques and big-data methods.
• Develop and implement process development roadmaps to meet yield milestones.
• Consolidate, interpret, and visualize diverse data sources to extract actionable yield insights.
• Perform fault isolation and failure analysis to determine root causes.
• Collaborate with design, test, and process teams to debug yield limiters and ensure manufacturability.
• Develop measurement recipes and harden equipment capabilities for advanced logic nodes.
• Execute new product introductions, design-technology co-optimization, and factory experiments.
• Create tools, algorithms, and systems for high-volume data analysis and yield modeling.
• Drive cross-functional actions to resolve yield, design, and manufacturing issues.

Requirements

Minimum technical requirements and preferred skills.

Must-have:

• 3+ years' experience in semiconductor failure analysis or test engineering.
• Strong understanding of array architecture and failure mechanisms, or hands-on experience with SCAN/ATPG methodology including scan-chain diagnosis, ATPG pattern generation and debug, and fault models (stuck-at, transition, path delay, bridging).
• Proficiency in fault isolation techniques, including electrical fault isolation (EFI), circuit and layout analysis.
• Experience debugging logic and memory/array failures from silicon bring-up through production and correlating ATE test results with design/process data.
• Experience with tester platforms (e.g., Advantest, Teradyne).
• Understanding of DFT (Design for Testability) concepts and implementation.
• Strong analytical, communication, and cross-functional collaboration skills; ability to manage multiple debug cases.

Nice-to-have:

• Experience with embedded memory compilers and array redundancy analysis.
• Familiarity with statistical analysis tools (JMP, Python, R) and exposure to ML-based fault classification or yield analysis.
• Experience with nanometer process nodes (7nm, 5nm, 3nm or below).
• Background in BIST for memory and logic.

Education Requirements

Bachelor's degree in Electronic Engineering, Computer Engineering, or a related field (as specified in the posting).

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.