VP of Systems

Job Title

VP of Systems

Role Summary

Lead development of Neurophos' inference servers and racks, owning electrical, mechanical, and systems engineering from board-level design through full system bring-up and qualification. Reports to the SVP of Engineering and builds and leads the Systems team responsible for product delivery, schedule, and budget.

Work on photonics-based AI hardware to improve energy efficiency for large-scale inference deployments.

Experience Level

Senior — requires 15+ years of hardware development and system-level engineering experience.

Responsibilities

Deliver full-scale inference server and rack products, from boards and interconnect to rack integration, bring-up, and qualification.

• Design and deliver accelerator baseboards, module carriers, front-panel boards, and the electrical interfaces between modules.
• Define and manage the PCIe host interface and scale-out fabric (leaf/TOR topology, oversubscription, intra-rack cabling, frontend and management networks).
• Own end-to-end power architecture from rack DC inlet to point-of-load, including regulation, transient budgets, and protection coordination.
• Own end-to-end high-speed channel budgets across full links (PCIe Gen6/7, 800G+ Ethernet) and perform channel closure.
• Lead hardware/firmware/software system bring-up, board/system validation, and qualification.
• Define and enforce system RAS (reliability, availability, serviceability) budgets and flowdown to modules.
• Build and lead the Systems organization; own program schedule, budget, staffing, and EVT/DVT/PVT phase gates and sign-off.

Requirements

Must-have technical and leadership qualifications.

• 15+ years of hardware development experience with demonstrated leadership and direct line management experience.
• Proven track record shipping server/rack products at volume through an OEM/ODM/CM or hyperscaler/DGX-class program with design ownership.
• System-level fluency from component/PCB through full server-node assembly and validation (L1–L10).
• Extensive NPI experience: owned EVT/DVT/PVT gates, spin decisions, and qualification processes.
• Board and system electrical expertise: layout direction, on-board power, SI/PI, high-speed interfaces (PCIe Gen6/7, Ethernet/OSFP), and validation.
• End-to-end channel and power-closure experience, including owned link budgets for high-speed interfaces and complete power architectures.
• Comfortable owning deep electrical authority while designing to interface definitions and product envelopes set by other teams.
• System-architecture ownership for rack/tray/board designs and experience with program management and staffing.

Education Requirements

BS or MS in Electrical Engineering or Mechanical Engineering, or equivalent practical experience/track record.

About the Company

Company: Neurophos

Headquarters: Sunnyvale, California, United States

Startup developing silicon-photonic AI accelerator chips that use programmable metasurfaces and dense optical cells to perform matrix multiplications at the speed of light, targeting large-scale AI inference with much higher energy efficiency and performance than traditional electronic approaches.