VLSI Verification Team Leader

Job Title

VLSI Verification Team Leader

Role Summary

Lead and grow a small verification team responsible for full-chip verification of a purpose-built analytics ASIC. The role combines hands-on verification work with technical and people leadership to deliver robust SystemVerilog/UVM-based verification environments and closure of full-chip verification plans.

Experience Level

Senior — requires substantial industry experience; the posting specifies 10+ years of verification experience and 2+ years leading a team.

Responsibilities

Primary responsibilities include technical leadership, verification strategy, and team development.

• Lead and mentor a team of verification engineers (technical guidance and personal mentoring).
• Define and execute full-chip verification plans and schedules across the development cycle.
• Design, develop, and maintain SystemVerilog/UVM verification environments and testbenches.
• Drive defect analysis, coverage closure, and sign-off criteria for blocks and full-chip integration.
• Coordinate with design, architecture, and validation teams to resolve verification issues and align on deliverables.
• Provide status reporting, risk assessment, and continuous process improvements for the verification flow.

Requirements

Must-have technical skills and experience; additional desirable skills are listed after must-haves.

• 10+ years of industry experience in verification and full-chip development cycle.
• 2+ years of experience leading an engineering team, including technical and personal mentoring.
• Proven hands-on experience with SystemVerilog and UVM methodology (required).

• Nice-to-have: Formal verification experience.
• Scripting skills in Python, Perl, or shell.
• Hands-on experience with two or more of: PCIe (Gen5+), DDR (v4+), AMBA family (AXI4+, ACE/CHI), ARM core architecture.

Education Requirements

BSc in Electronics Engineering or Computer Science is specified. An M.Sc. in Electronics Engineering or Computer Science is listed as an advantage. No mention of alternative-equivalent experience language.

About the Company

Company: Speedata

Speedata develops a purpose-built ASIC, the Analytics Processing Unit (APU), to accelerate analytics and AI data workloads (e.g., Apache Spark), improving query performance and reducing infrastructure TCO by executing analytics operations in silicon.