VLSI Physical Design Engineer

Job Title

VLSI Physical Design Engineer

Role Summary

Design and implement physical layouts for complex ASIC/VLSI designs, focusing on timing closure, synthesis, and full-chip physical implementation. Work on a hybrid engineering team that partners with architecture, DFT, signal integrity, and external physical-design partners to deliver production-ready ASICs.

This role is operational and technical; expected to drive implementation, improve flows, and mentor junior engineers.

Experience Level

Mid-level. The posting requests roughly 1–6 years of relevant VLSI design, verification, or implementation experience.

Responsibilities

Primary hands-on responsibilities include analysis, implementation, and verification of physical design and timing for partition and full-chip designs.

• Perform static timing analysis (partition and full-chip) and timing signoff.
• Create, validate, and maintain timing constraints and timing budgets.
• Drive timing closure for setup, hold, clock, I/O, and test timing; analyze timing reports and fix critical paths.
• Perform synthesis, netlist quality checks, and formal verification.
• Support chip partitioning, floorplanning, and physical design implementation.
• Create and manage functional engineering change orders (ECOs).
• Develop flow automation and methodology improvements for synthesis, timing analysis, formal verification, physical design, and signoff; often using AI techniques to improve methodologies.
• Partner with cross-functional teams and external physical-design partners to close timing and complete back-end flows.
• Review projects for compliance with ASIC technology, methodology, and development standards.
• Provide technical guidance and mentoring to less-experienced engineers.

Requirements

Key technical skills and experience required or strongly expected.

• Must-have: 1–6 years of experience in VLSI design, verification, or implementation.
• Must-have: Strong knowledge of electrical engineering fundamentals, digital logic, VLSI principles, and computer architecture.
• Must-have: Hands-on experience with static timing analysis, timing constraints, timing closure, synthesis, netlist quality analysis, and ECO implementation.
• Must-have: Experience with industry-standard EDA tools (examples: Synopsys Fusion Compiler, Design Compiler, PrimeTime, Formality; Cadence Genus, RTL Compiler, LEC).
• Must-have: Programming/scripting and hardware description language (HDL) skills for flow automation.
• Must-have: Strong analytical, problem-solving, and communication skills.
• Nice-to-have: Experience with formal verification tools, DFT, signal integrity, or applying AI to methodology improvements.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a closely related technical field, or equivalent practical experience; coursework or hands-on experience in VLSI design is expected.

About the Company

Company: Hewlett Packard Enterprise

Headquarters: Spring, TX, United States

Global enterprise technology company delivering hybrid cloud, edge-to-cloud platforms, servers, storage, networking, and IT services to help organizations build, run, and secure applications and infrastructure at scale.