VLSI Optimization Engineer (Neihu)

Job Title

VLSI Optimization Engineer (Neihu)

Role Summary

Build automation and AI-assisted tools to address VLSI design and physical layout challenges, with emphasis on sign-off quality and design–technology co-optimization (DTCO). The role sits within an ASIC/physical design engineering organization and focuses on rapid prototyping and deployment of scalable software solutions.

Work closely with design, layout, and verification teams to translate physical constraints into automated workflows and tools.

Experience Level

Entry-level / Early-career. Candidates commonly have up to 4 years of relevant experience; more experienced applicants will also be considered.

Responsibilities

The role involves developing automation, applying algorithmic techniques, and integrating physical verification awareness into tools.

• Collaborate with cross-functional teams to gather requirements and understand design and layout constraints.
• Design, implement, and maintain automation tools to improve VLSI design productivity.
• Use AI-assisted development tools (e.g., code generation, AI agents) to accelerate prototyping and implementation.
• Incorporate physical design and verification requirements, including DRC, LVS, and basic parasitic/sign-off considerations.
• Analyze DTCO and trade-offs across design and process domains.
• Write clean, maintainable, and scalable code with attention to debugging and problem decomposition.

Requirements

Must-have technical skills and experience required for the role.

• Strong programming skills in Python or similar languages.
• Experience with Linux/Unix development environments.
• Solid foundation in data structures, algorithms, and general mathematical problem-solving.
• Basic understanding of VLSI design fundamentals (CMOS, circuits, or physical design concepts) and physical verification concepts (DRC, LVS, sign-off flows).
• Exposure to AI-assisted development tools and scripting automation.
• Familiarity with constraint-based problem solving concepts (CSP) and conceptual knowledge of ILP / SAT / SMT approaches.

Nice-to-have:

• Hands-on project or internship experience in VLSI CAD/EDA, layout, or physical design automation.
• Familiarity with layout data formats, design rules, or basic EDA tools.
• Experience applying optimization techniques and algorithmic problem-solving to practical problems.
• Experience using AI tools to improve coding productivity.
• Good communication and teamwork skills.

Education Requirements

Bachelor's or Master’s degree in Electrical Engineering, Computer Science, Science, Engineering, or a related technical field. The posting lists a Bachelor's degree as a minimum qualification and references Master's as acceptable.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.