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VLSI Design Verification Manager - Slingshot ASIC Team

Hewlett Packard Enterprise
May 19, 2026
Full-time
On-site
Fort Collins, Colorado, United States
$135,000 - $310,500 USD yearly
Verification Jobs, Level - Senior

Job Title

VLSI Design Verification Manager - Slingshot ASIC Team

Role Summary

Lead design verification for HPE Slingshot networking ASICs used in NIC and switch products. Manage a team of approximately 8–15 verification engineers, own verification methodology and execution quality, and drive sign‑off readiness in coordination with logic design and architecture teams.

Onsite role based in Fort Collins, CO. The position combines technical leadership, people development, and program execution.

Experience Level

Senior — typically requires 10+ years of VLSI design verification experience with strong hands‑on pre‑silicon DV background.

Responsibilities

Primary responsibilities include defining verification strategy, delivering quality verification results, and developing the verification team.

  • Provide leadership for all phases of pre‑silicon design verification: verification planning, testbench development, coverage closure, regression management, and sign‑off reviews.
  • Define, own, and evolve design verification methodology across block, subsystem, and full‑chip scopes.
  • Ensure development of robust SystemVerilog/UVM environments, including stimulus, scoreboards, checkers, assertions, and functional coverage.
  • Drive regression health, perform failure triage and root‑cause isolation, and close design issues with logic design and architecture teams.
  • Manage project deliverables, schedules, and staffing to meet program milestones and quality goals.
  • Recruit, mentor, and develop engineering staff; set performance expectations and support career growth.
  • Identify and implement process improvements, reuse, automation, and efficiency gains in verification workflows.
  • Communicate verification status, risks, and readiness to management and cross‑functional partners.

Requirements

Key technical and leadership requirements. Education requirements are listed separately below.

  • Must-have: Strong understanding of SystemVerilog and UVM‑based verification methodologies; demonstrated technical leadership in design verification; experience with verification planning, coverage‑driven verification, regression management, and sign‑off readiness; proficiency with industry EDA simulation tools; strong analytical, problem‑solving, and communication skills; ability to work effectively in a multi‑site, cross‑functional engineering environment.
  • Nice-to-have: Prior people‑management experience (hiring, coaching, performance management); direct experience with Synopsys VCS large‑scale regression execution and triage workflows; familiarity with GitHub Enterprise Cloud workflows and AI tools; familiarity with high‑performance networking (Ethernet), SERDES, PCIe, or HPC/AI systems; experience improving verification efficiency through automation and reuse.

Education Requirements

Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent technical field, or equivalent practical experience.


About the Company

Company: Hewlett Packard Enterprise

Headquarters: Spring, TX, United States

Global enterprise technology company delivering hybrid cloud, edge-to-cloud platforms, servers, storage, networking, and IT services to help organizations build, run, and secure applications and infrastructure at scale.

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Date Posted: 2026-05-19