VLSI Design Engineer

Job Title

VLSI Design Engineer

Role Summary

The VLSI Design Engineer will design digital ASIC/SoC blocks from micro-architecture through RTL and synthesis, collaborating with algorithm, verification, DFT and backend teams. The role focuses on producing synthesis- and timing-friendly RTL for high-performance communication systems.

This is an engineering role on a chip-design team responsible for implementation quality, timing closure, and integration into larger systems. A practical, results-oriented approach is expected.

Experience Level

Senior — requires 5+ years of ASIC/VLSI digital design experience.

Responsibilities

Primary responsibilities include the full digital design flow, cross-functional collaboration, and design validation.

• Translate algorithms and architecture into efficient hardware micro-architectures and RTL.
• Implement RTL using Verilog/SystemVerilog with synthesis- and timing-aware coding practices.
• Interpret and apply protocol specifications (e.g., Ethernet) in designs.
• Develop synthesis constraints (SDC), run synthesis, and analyze timing reports.
• Work with verification teams on testbenches, debug support, and coverage closure.
• Coordinate with DFT and backend teams for scan insertion, ATPG/BIST support, floorplanning, and timing closure.
• Participate in design reviews and defend design decisions; maintain clear design documentation.
• Debug functional and timing issues in pre- and post-silicon phases; support silicon bring-up and validation when applicable.
• Optimize designs for area, power, and performance (PPA) and contribute to IP/SoC integration.
• Stay current with EDA tools, verification methodologies, and industry best practices.

Requirements

Required and preferred technical skills and attributes.

• Must-have: 5+ years ASIC/VLSI digital design experience; strong Verilog/SystemVerilog skills; experience with simulation tools and verification methodologies; experience with synthesis and timing analysis; strong collaboration and communication skills; self-motivated and able to work independently.
• Nice-to-have: Experience with CDC, linting, formal verification, low-power design techniques, DFT (scan, ATPG, BIST); DSP-oriented block design experience; high-speed Ethernet (100G+) design experience; scripting for automation (Python, Perl, TCL).

Education Requirements

BS or MS in Electrical Engineering or Computer Engineering (from leading universities). Equivalent practical experience not explicitly stated.

About the Company

Company: Retym Israel

Technology company hiring VLSI/ASIC digital design engineers for communication systems and SoC/IP development. Work includes RTL design, verification, synthesis, timing closure, and silicon bring-up.