Video Codec Digital Circuit Design Engineer

Job Title

Video Codec Digital Circuit Design Engineer

Role Summary

Design and optimize digital hardware blocks for video codecs and integrate codec IP into SoC subsystems. The role partners with system, verification, physical design, and firmware teams to deliver RTL, models, and support for pre‑ and post‑silicon validation.

Experience Level

Mid-level. Typical hires have experience across a range (approximately 2–8 years) in ASIC or digital design for multimedia/video systems.

Responsibilities

Primary engineering responsibilities for the video codec datapath and SoC integration.

• Architect, micro-architect, and implement digital hardware blocks for video encode/decode (motion estimation/compensation, transform/quantization, entropy coding, in-loop filters, rate control datapaths).
• Translate video standard requirements (H.264/AVC, H.265/HEVC, AV1, VVC) into scalable, configurable hardware microarchitectures.
• Develop C/C++/SystemC models for performance, accuracy, and power estimation and perform algorithm-to-hardware decomposition to guide RTL.
• Collaborate with systems and architecture teams to evaluate codec KPIs: throughput, latency, memory bandwidth, and quality metrics.
• Define verification plans, functional coverage, and debug infrastructure with verification teams for robust pre-silicon validation.
• Drive integration of codec IP with memory subsystems, firmware interfaces, and on-chip networks (NoC/fabric).
• Work with physical design teams on timing-aware microarchitecture, pipeline optimization, and clock/power domain planning to meet PPA targets.
• Support post-silicon bring-up, analyze silicon performance, and recommend architectural or firmware updates as needed.

Requirements

Core technical skills and domain experience required to perform the role. Education requirements are listed separately below.

• Must-have: Proven experience in digital/ASIC design for video codecs or related multimedia datapaths and familiarity with relevant standards (H.264/AVC, H.265/HEVC, AV1, VVC).
• Strong RTL design and implementation skills; experience with performance-driven microarchitecture and pipeline optimization.
• Experience building and using C/C++/SystemC models for performance, accuracy, and power analysis.
• Experience collaborating with system architecture, verification, physical design, and firmware teams for IP integration and validation.
• Experience in pre-silicon verification planning and post-silicon debugging.
• Familiarity with memory subsystem interactions, NoC/fabric interfaces, and SoC integration concerns.
• Nice-to-have: Prior ASIC/SoC experience in multimedia products, knowledge of PPA trade-offs in physical design, or background in motion estimation/quality metric analysis.

Education Requirements

Bachelor's degree in Science, Engineering, or a related field.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.