Verification / Senior Verification Engineer

Job Title

Verification / Senior Verification Engineer

Role Summary

Join a hardware and embedded-software engineering team to deliver fully verified, high-performance, trusted systems. You will own verification end-to-end across block and system levels and shape how quality and reliability are built into the product.

Background in quantum computing is not required; you will learn domain specifics on the job.

Experience Level

Senior-level. The posting requires demonstrable commercial experience in functional verification but does not specify an exact years-of-experience threshold.

Responsibilities

The role requires ownership of verification strategy and implementation across designs and platforms.

• Define verification plans and detailed test strategies in collaboration with designers and architects.
• Design and implement scalable SystemVerilog testbenches, checkers, reference models and coverage groups.
• Develop self-testing, directed and randomised tests to validate block- and system-level behaviour.
• Maintain and evolve the verification environment; track regressions, coverage metrics and bugs.
• Debug issues across RTL, simulation and hardware; close verification cycles to release-ready quality.
• Communicate verification status and risks to stakeholders and incorporate feedback from cross-functional teams.

Requirements

Must-have skills and attributes for successful performance.

• Commercial experience in functional verification, including ownership of verification planning and strategy.
• Experience designing testbenches with verification frameworks such as UVM/OVM.
• Knowledge of SystemVerilog assertions (SVA).
• Experience with programming languages such as C, C++ and Python.
• Proven ability to debug across RTL, simulators and hardware platforms.
• Proactive, able to define scope independently and work with ambiguous requirements.
• Strong collaboration and communication skills; able to give and receive constructive feedback.

Nice-to-have:

• Formal verification experience.

Education Requirements

Not specified.

About the Company

Company: Riverlane

Headquarters: Cambridge, UK

Riverlane develops quantum error correction (QEC) technology to enable fault-tolerant quantum computing. The Cambridge-based company builds hardware and software solutions and partners with quantum hardware providers and government agencies to accelerate R&D and deploy low-latency, high-throughput control systems for quantum experiments.