Verification Engineer - Networking

Role Overview

This position is for a Verification Engineer involved in the comprehensive testing of next generation Data Center network products at AMD. You will utilize the latest UVM standards and create extensive test plans to ensure coverage closure across various ASIC design stages.

Position Summary

The Verification Engineer will enhance Data Center Networking solutions, a crucial segment of AMD's business, serving leading internet and cloud companies. You will work collaboratively with design and architecture teams and may need to travel for project-related activities.

Experience Level

This is a technical role suitable for those who are adept at engaging both independently and as part of a team, with a strong focus on innovation, quality control, and meeting set timelines.

Primary Responsibilities

• Collaborate with architects and engineers to validate new features.
• Create and maintain detailed test plan documentation outlining feature interactions.
• Estimate times for developing required tests and adjusting the testing environment.
• Construct both directed and random verification tests.
• Analyze test failures to identify root causes while collaborating with RTL and firmware engineers for resolutions.
• Review coverage metrics and update tests as needed to meet requirements.

Candidate Requirements

• Expertise in IP level ASIC verification and debugging firmware/RTL code.
• Strong knowledge of UVM/SV testbenches and programming in Verilog, System Verilog, C, and C++.
• Experience with PCIe and/or Ethernet protocols.
• Background in automating workflows within distributed computing environments.
• Ability to utilize scripting languages such as Python, Ruby, Makefile, and shell.
• Leadership or mentorship experience is advantageous.
• Prior familiarity with network processors is beneficial.

Education Requirements

A Bachelor's or Master's degree in Computer Engineering or Electrical Engineering is required.